Datasheet
LPC1315_16_17_45_46_47 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 20 September 2012 27 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
7.8.1 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
• Port interrupts can be triggered by any pin or pins in each port.
7.9 USB interface
Remark: The USB interface is available on parts LPC1345/46/47 only.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1345/46/47 USB interface consists of a full-speed device controller with on-chip
PHY (PHYsical layer) for device functions.
Remark: Configure the LPC1345/46/47 in default power mode with the power profiles
before using the USB (see Section 7.18.5.1
). Do not use the USB with the part in
performance, efficiency, or low-power mode.
7.9.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
7.9.1.1 Features
• Dedicated USB PLL available.
• Fully compliant with USB 2.0 specification (full speed).
• Supports 10 physical (5 logical) endpoints including one control endpoint.
• Single and double buffering supported.
• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
• Supports wake-up from Deep-sleep mode and Power-down mode on USB activity
and remote wake-up.
• Supports SoftConnect.
• Supports Link Power Management (LPM).
7.10 USART
The LPC1315/16/17/45/46/47 contains one USART.