Datasheet

LPC1315_16_17_45_46_47 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 20 September 2012 2 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
 Debug options:
 Standard JTAG test interface for BSDL.
 Serial Wire Debug.
 Support for ETM ARM Cortex-M3 debug time stamping.
 Digital peripherals:
 Up to 51 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, input inverter, and pseudo open-drain mode. Eight pins
support programmable glitch filter.
 Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
 Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
 High-current source output driver (20 mA) on one pin (P0_7).
 High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
 Four general purpose counter/timers with a total of up to 8 capture inputs and 13
match outputs.
 Programmable Windowed WatchDog Timer (WWDT) with a internal low-power
WatchDog Oscillator (WDO).
 Repetitive Interrupt Timer (RI Timer).
 Analog peripherals:
 12-bit ADC with eight input channels and sampling rates of up to 500 kSamples/s.
 Serial interfaces:
 USB 2.0 full-speed device controller (LPC1345/46/47) with on-chip ROM-based
USB driver library.
 USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
 Two SSP controllers with FIFO and multi-protocol capabilities.
 I
2
C-bus interface supporting the full I
2
C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
 Clock generation:
 Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator)
with failure detector.
 12 MHz high-frequency Internal RC oscillator (IRC) trimmed to 1 % accuracy over
the entire voltage and temperature range. The IRC can optionally be used as a
system clock.
 Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
 PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
 A second, dedicated PLL is provided for USB (LPC1345/46/47).
 Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
 Power control:
 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
 Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.