Datasheet

LPC1311_13_42_43 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 June 2012 55 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
10.7 SSP0/1 interface
Remark: The SSP1 interface is available on the LPC1313FBD48/01 only.
[1] T
cy(clk)
= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the
main clock frequency f
main
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] T
amb
= −40 °C to +85 °C.
[3] T
cy(clk)
= 12 × T
cy(PCLK)
.
[4] T
amb
= 25 °C; V
DD
= 3.3 V.
Table 19. Dynamic characteristics: SSP pins in SPI mode
Symbol Parameter Conditions Min Max Unit
SSP master
T
cy(clk)
clock cycle time full-duplex mode
[1]
40 - ns
when only transmitting
[1]
27.8 - ns
t
DS
data set-up time in SPI mode;
2.4 V ≤ V
DD
≤ 3.6 V
[2]
15 - ns
2.0 V ≤ V
DD
< 2.4 V
[2]
20 - ns
t
DH
data hold time in SPI mode
[2]
0- ns
t
v(Q)
data output valid time in SPI mode
[2]
-10ns
t
h(Q)
data output hold time in SPI mode
[2]
0- ns
SSP slave
T
cy(PCLK)
PCLK cycle time 13.9 - ns
t
DS
data set-up time in SPI mode
[3][4]
0- ns
t
DH
data hold time in SPI mode
[3][4]
3 × T
cy(PCLK)
+ 4 - ns
t
v(Q)
data output valid time in SPI mode
[3][4]
-3 × T
cy(PCLK)
+ 11 ns
t
h(Q)
data output hold time in SPI mode
[3][4]
-2 × T
cy(PCLK)
+ 5 ns