Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 32-Bit 72 MHz I/O number 42

1. General description

The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash

memory, up to 8 kB of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus

C-bus interface, one UART, four general purpose timers, and up to 42 general purpose

I/O pins.

Remark: The LPC1311/13/42/43 series consists of the LPC1300 series (parts

LPC1311/13/42/43) and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The

LPC1300L series features the following enhancements over the LPC1300 series:

• Power profiles with lower power consumption in Active and Sleep modes.

• Four levels for BOD forced reset.

• Second SSP controller (LPC1313FBD48/01 only).

• Windowed Watchdog Timer (WWDT).

• Internal pull-up resistors pull up pins to full V

level.

• Programmable pseudo open-drain mode for GPIO pins.

2. Features and benefits

 ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming

memory.

 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 Selectable boot-up: UART or USB (USB on LPC1342/43 only).

 On LPC1342/43: USB MSC and HID on-chip drivers.

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and

8 kB SRAM; USB device

Rev. 5 — 6 June 2012 Product data sheet

Summary of content (74 pages)

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LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device Rev. 5 — 6 June 2012 Product data sheet 1. General description The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  Serial interfaces:  USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43 only).  UART with fractional baud rate generation, modem, internal FIFO, and RS-485/EIA-485 support.  SSP controller with FIFO and multi-protocol capabilities.  Additional SSP controller on LPC1313FBD48/01.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  Unique device serial number for identification.  Available as 48-pin LQFP package and 33-pin HVQFN package. 3. Applications     eMetering Lighting Alarm systems White goods 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1311FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 2.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 37 PIO3_1 38 PIO2_3/RI 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO1_11/AD7 44 VDD 43 PIO3_2 45 PIO1_5/RTS/CT32B0_CAP0 46 PIO1_6/RXD/CT32B0_MAT0 47 PIO1_7/TXD/CT32B0_MAT1 48 PIO3_3 6.
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LPC1311/13/42/43 NXP Semiconductors PIO1_7/TXD/CT32B0_MAT1 PIO1_6/RXD/CT32B0_MAT0 PIO1_5/RTS/CT32B0_CAP0 VDD PIO3_2 PIO1_11/AD7 PIO1_4/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO1_3/AD4/CT32B1_MAT2 31 30 29 28 27 26 25 terminal 1 index area 32 32-bit ARM Cortex-M3 microcontroller PIO2_0/DTR 1 24 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE 3 22 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 4 21 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20
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LPC1311/13/42/43 NXP Semiconductors 37 PIO3_1 38 PIO2_3/RI/MOSI1(1) 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 41 VSS 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 42 PIO1_11/AD7 43 PIO3_2 44 VDD 45 PIO1_5/RTS/CT32B0_CAP0 46 PIO1_6/RXD/CT32B0_MAT0 47 PIO1_7/TXD/CT32B0_MAT1 48 PIO3_3 32-bit ARM Cortex-M3 microcontroller PIO2_6 1 36 PIO3_0 PIO2_0/DTR/SSEL1(1) 2 35 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 R/PIO1_0/AD1/CT32B1_CAP0 VSS 5 XTALIN 6 XT
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LPC1311/13/42/43 NXP Semiconductors VDD PIO3_2 PIO1_11/AD7 PIO1_4/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO1_3/AD4/CT32B1_MAT2 27 26 25 PIO1_5/RTS/CT32B0_CAP0 28 PIO1_6/RXD/CT32B0_MAT0 30 29 PIO1_7/TXD/CT32B0_MAT1 31 terminal 1 index area 32 32-bit ARM Cortex-M3 microcontroller 7 33 VSS 18 PIO0_9/MOSI0/CT16B0_MAT1/SWO PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0 16 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 PIO0_7/CTS 19 15 6 14 PIO1_10/AD6/CT16B1_MAT1 VDD PIO3_
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6.2 Pin description Table 3. LPC1313/42/43 LQFP48 pin description table Symbol RESET/PIO0_0 PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE Pin 3[2] 4[3] Start logic input Type Reset Description state yes I I; PU RESET — External reset input with 20 ns glitch filter.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. LPC1313/42/43 LQFP48 pin description table …continued Symbol Pin Start logic input PIO2_10 25[3] yes PIO2_11/SCK0 31[3] PIO3_0/DTR PIO3_1/DSR PIO3_2/DCD PIO3_3/RI 36[3] yes yes 37[3] yes 43[3] yes 48[3] yes Type Reset Description state [1] I/O I; PU PIO2_10 — General purpose digital input/output pin. I/O I; PU PIO2_11 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SSP0.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. LPC1311/13/42/43 HVQFN33 pin description table …continued Symbol Pin Start Type Reset Description logic state [1] input PIO1_7/TXD/ CT32B0_MAT1 32[3] yes PIO1_8/ CT16B1_CAP0 7[3] PIO1_9/ CT16B1_MAT0 12[3] PIO1_10/AD6/ CT16B1_MAT1 20[5] PIO1_11/AD7 27[5] yes PIO2_0/DTR 1[3] PIO3_2 28[3] yes PIO3_4 13[3] PIO3_5 14[3] yes yes I/O I; PU PIO1_7 — General purpose digital input/output pin.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code).
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4 GB AHB peripherals LPC1311/13/42/43 0x5020 0000 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 16 - 127 reserved 0xE000 0000 0x5004 0000 12-15 GPIO PIO3 0x5020 0000 8-11 GPIO PIO2 0x5000 0000 4-7 GPIO PIO1 0-3 GPIO PIO0 reserved AHB peripherals 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 reserved APB peripherals 0x4008 0000 23 - 31 reserved 0x4008 0000 1 GB APB peripherals 0x4005 C000 22 SSP1 (
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.6.1 Features • Controls system exceptions and peripheral interrupts. • On the LPC1311/13/42/43, the NVIC supports up to 17 vectored interrupts. In addition, up to 40 of the individual GPIO inputs are NVIC-vector capable. • 8 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table. • Software interrupt generation. 7.6.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • On the LPC1311/13/42/43, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 2.6 V (VDD = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block. • On the LPC1311/01 and LPC1313/01, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block. 7.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.10 UART The LPC1311/13/42/43 contains one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.10.1 Features • • • • • Maximum UART data bit rate of 4.5 MBit/s. 16-byte receive and transmit FIFOs.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory).
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.14 General purpose external event counter/timers The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 224 × 4) in multiples of Tcy(WDCLK) × 4. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of watchdog operation under different power reduction conditions.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller AHB clock 0 (system) system clock SYSTEM CLOCK DIVIDER AHB clock 1 (ROM) AHBCLKCTRL (AHB clock enable) AHB clocks 2 to 15 (memories and peripherals) 14 AHBCLKCTRL AHB clock 16 (IOCONFIG) AHBCLKCTRL 2 IRC oscillator SSP0/1 PERIPHERAL CLOCK DIVIDER SSP0/1 UART PERIPHERAL CLOCK DIVIDER UART main clock watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator ARM TRACE CLOCK DIVIDER ARM trace clock SYSTICK TIMER
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.18.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC1342/43, the system oscillator must be used to provide the clock source to USB.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.18.5 Power control The LPC1311/13/42/43 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.18.5.4 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the WAKEUP pin. A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode. When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller There are three levels of Code Read Protection: 1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 256 word boundary. 7.20 Emulation and debugging Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported. LPC1311_13_42_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 June 2012 © NXP B.V. 2012.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions VDD supply voltage (core and external rail) VI input voltage 5 V tolerant I/O pins; only valid when the VDD supply voltage is present [2] Min Max Unit 2.0 3.6 V −0.5 +5.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9. Static characteristics Table 7. Static characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter VDD Min Typ[1] Max Unit 2.0 3.3 3.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 7. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage VDD − 0.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 7. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOH 2.5 V ≤ VDD ≤ 3.6 V; VOH = VDD − 0.4 V 20 - - mA 2.0 V ≤ VDD < 2.5 V; VOH = VDD − 0.4 V; 12 - - mA 2.5 V ≤ VDD ≤ 3.6 V; VOL = 0.4 V 4 - - mA 2.0 V ≤ VDD < 2.5 V; VOL = 0.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 7. Static characteristics …continued Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit [17] 2.8 - 3.5 V [17] - - 20 pF 36 - 44.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 8. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 8.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9.1 BOD static characteristics for LPC1300 series Remark: Applies to parts LPC1311/13/42/43 and all their packages. Table 9. BOD static characteristics[1] Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit Vth threshold voltage interrupt level 0 assertion - 1.69 - V de-assertion - 1.84 - V assertion - 2.29 - V de-assertion - 2.44 - V interrupt level 1 interrupt level 2 assertion - 2.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9.2 BOD static characteristics for LPC1300L series (LPC1311/01 and LPC1313/01) Remark: Applies to parts LPC1311/01 and LPC1313/01 and all packages. Table 10. BOD static characteristics[1] Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit Vth threshold voltage interrupt level 0 assertion - 1.65 - V de-assertion - 1.80 - V interrupt level 1 assertion - 2.22 - V de-assertion - 2.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aae993 18 IDD (mA) 72 MHz 15 12 9 48 MHz 36 MHz 24 MHz 6 12 MHz 3 2.0 2.4 2.8 3.2 3.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aae995 10 72 MHz IDD (mA) 8 48 MHz 6 36 MHz 4 24 MHz 12 MHz 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC1342/43).
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aae996 1.2 IDD (μA) 0.6 VDD = 3.6 V 3.3 V 2.0 V 0.4 0 −40 −15 10 35 60 85 temperature (°C) Fig 13. Typical supply current versus temperature in Deep power-down mode (LPC1311/13/42/43) 9.4 Power consumption for LPC1300L series (LPC1311/01 and LPC1313/01) Remark: Applies to parts LPC1311/01 and LPC1313/01 and all their packages.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag235 16 IDD (mA) 72 MHz 12 8 48 MHz 36 MHz 4 24 MHz 12 MHz 0 2.0 2.4 2.8 3.2 3.6 VDD (V) Conditions: Tamb = 25 °C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; low-current mode. Fig 14.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag237 8 72 MHz IDD (mA) 6 48 MHz 4 36 MHz 24 MHz 2 12 MHz 0 ˗40 ˗15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; low-current mode. Fig 16.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag239 0.6 IDD (µA) VDD = 3.6 V 3.3 V 2.0 V 0.4 0.2 0 ˗40 ˗15 10 35 60 85 temperature (°C) Fig 18. Typical supply current versus temperature in Deep power-down mode (LPC1311/01 and LPC1313/01) 9.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Power consumption for individual analog and digital blocks …continued Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz 72 MHz GPIO - 0.21 0.80 1.17 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. IOCONFIG - 0.00 0.02 0.02 - I2C - 0.03 0.12 0.17 - ROM - 0.04 0.15 0.22 - SSP0 - 0.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aaf019 60 T = 85 °C 25 °C −40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 20. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae991 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 21.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 22. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 23.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 24. Typical pull-down current Ipd versus input voltage Vi LPC1311_13_42_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 June 2012 © NXP B.V. 2012. All rights reserved.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10. Dynamic characteristics 10.1 Power-up ramp conditions Table 12. Power-up characteristics Tamb = −40 °C to +85 °C. Symbol Parameter tr rise time twait wait time VI input voltage Conditions at t = t1: 0 < VI ≤ 400 mV [1] [1][2] at t = t1 on pin VDD Min Typ Max Unit 0 - 500 ms 12 - - μs 0 - 400 mV [1] See Figure 25.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.3 External clock Table 14. Dynamic characteristic: external clock Tamb = −40 °C to +85 °C; VDD over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) × 0.4 - - ns tCLCX clock LOW time Tcy(clk) × 0.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.4 Internal oscillators Table 15. Dynamic characteristics: IRC Tamb = −40 °C to +85 °C; 2.7 V ≤ VDD ≤ 3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.5 I/O pins Table 17. Dynamic characteristics: I/O pins[1] Tamb = −40 °C to +85 °C; 3.0 V ≤ VDD ≤ 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 10.6 I2C-bus Table 18. Dynamic characteristic: I2C-bus pins[1] Tamb = −40 °C to +85 °C.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [8] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.7 SSP0/1 interface Remark: The SSP1 interface is available on the LPC1313FBD48/01 only. Table 19. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter Conditions Min Max Unit clock cycle time full-duplex mode [1] 40 - ns when only transmitting [1] 27.8 - ns in SPI mode; [2] 15 - ns [2] 20 - ns SSP master Tcy(clk) data set-up time tDS 2.4 V ≤ VDD ≤ 3.6 V 2.0 V ≤ VDD < 2.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 29. SSP master timing in SPI mode LPC1311_13_42_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 6 June 2012 © NXP B.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tclk(H) tclk(L) tDS tDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 th(Q) CPHA = 0 DATA VALID 002aae830 Fig 30. SSP slave timing in SPI mode LPC1311_13_42_43 Product data sheet All information provided in this document is subject to legal disclaimers. Rev.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.8 USB interface (LPC1342/43 only) Table 20. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD, unless otherwise specified. 3.0 V ≤ VDD ≤ 3.6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. Application information 11.1 Suggested USB interface solutions (LPC1342/43 only) VDD USB_CONNECT LPC134x soft-connect switch R1 1.5 kΩ USB_VBUS USB_DP RS = 33 Ω USB_DM USB-B connector RS = 33 Ω VSS 002aae608 Fig 32. LPC1342/43 USB interface on a self-powered device VDD LPC134x R1 1.5 kΩ USB_VBUS USB_DP RS = 33 Ω USB-B connector USB_DM RS = 33 Ω VSS 002aae609 Fig 33.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 34. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 34), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 21.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.5 Reset pad configuration VDD VDD VDD Rpu ESD 20 ns RC GLITCH FILTER reset PIN ESD VSS 002aaf274 Fig 37. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 8: • The ADC input trace must be short and as close as possible to the LPC1311/13/42/43 chip.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.7 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1343FBD48 in Table 23. Table 23. ElectroMagnetic Compatibility (EMC) for part LPC1343FBD48 (TEM-cell method) VDD = 3.3 V; Tamb = 25 °C.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A B D terminal 1 index area E A A1 c detail X e1 e 9 16 C C A B C v w b y y1 C L 8 17 e e2 Eh 33 1 terminal 1 index area 24 32 X 25 Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23 c D(1) Dh E(1) 0.2 7.1 7.0 6.9 4.85 4.70 4.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 13. Soldering Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 40.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of HVQFN33 package OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) W = 0.30 CU SPD = 1.00 SP LaE = 7.95 CU PIE = 7.25 PA+OA LbE = 5.80 CU evia = 4.25 evia = 1.05 0.45 DM SPE = 1.00 SP GapE = 0.70 SP 4.55 SR SEhtot = 2.70 SP EHS = 4.85 CU OwEtot = 5.10 OA OIE = 8.20 OA e = 0.65 0.45 DM GapD = 0.70 SP evia = 2.40 B-side SDhtot = 2.70 SP 4.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14. Abbreviations Table 24.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Revision history Table 25. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1311_13_42_43 v.5 20120606 Product data sheet - Modifications: LPC1311_13_42_43 v.4 • Parameters VOL, VOH, IOL, IOH updated for voltage range 2.0 V ≤ VDD < 2.5 V in Table 7. • Condition “The peak current is limited to 25 times the corresponding maximum current.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 18. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.7 7.8 7.8.1 7.9 7.9.1 7.9.1.1 7.10 7.10.1 7.11 7.11.1 7.12 7.12.1 7.13 7.13.1 7.14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . .
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LPC1311/13/42/43 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . .