Datasheet

LPC12D27 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 20 September 2011 9 of 46
NXP Semiconductors
LPC12D27
32-bit ARM Cortex-M0 microcontroller
PIO0_6/RI0/
CT32B1_CAP0/
CT32B1_MAT0
12
[2]
yes I; PU I/O PIO0_6 — General purpose digital input/output pin. Also serves
as wake-up pin from Deep-sleep mode.
I RI0
— Ring Indicator input for UART0.
I CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.
O CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.
PIO0_7/CTS0
/
CT32B1_CAP1/
CT32B1_MAT1
13
[2]
yes I; PU I/O PIO0_7 — General purpose digital input/output pin. Also serves
as wake-up pin from Deep-sleep mode.
I CTS0
— Clear To Send input for UART0.
I CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.
O CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.
PIO0_8/RXD1
/CT32B1_CAP2/
CT32B1_MAT2
14
[2]
yes I; PU I/O PIO0_8 — General purpose digital input/output pin. Also serves
as wake-up pin from Deep-sleep mode.
I RXD1 — Receiver input for UART1.
I CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.
O CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.
PIO0_9/TXD1/
CT32B1_CAP3/
CT32B1_MAT3
15
[2]
yes I; PU I/O PIO0_9 — General purpose digital input/output pin. Also serves
as wake-up pin from Deep-sleep mode.
O TXD1 — Transmitter output for UART1.
I CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1.
O CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.
PIO0_10/SCL 17
[3]
yes I; IA I/O PIO0_10 — General purpose digital input/output pin. Also serves
as wake-up pin from Deep-sleep mode.
I/O SCL — I
2
C-bus clock input/output.
PIO0_11/SDA/
CT16B0_CAP0/
CT16B0_MAT0
18
[3]
yes I; IA I/O PIO0_11 — General purpose digital input/output pin. Also serves
as wake-up pin from Deep-sleep mode.
I/O SDA — I
2
C-bus data input/output.
I CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.
O CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.
PIO0_12/CLKOUT/
CT16B0_CAP1/
CT16B0_MAT1
19
[7]
no I; PU I/O PIO0_12 — General purpose digital input/output pin. A LOW
level on this pin in during reset starts the ISP command handler.
High-current output driver.
O CLKOUT — Clock out pin.
I CT16B0_CAP1 — Capture input, channel 0 for 16-bit timer 0.
O CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.
RESET
/PIO0_13 20
[4]
no I; PU I RESET — External reset input: A LOW on this pin resets the
device, causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
I/O PIO0_13 — General purpose digital input/output pin.
PIO0_14/SCK 21
[2]
no I; PU I/O PIO0_14 — General purpose digital input/output pin.
I/O SCK — Serial clock for SSP.
Table 3. LPC12D27 LQFP100 pin description
…continued
Symbol Pin Start
logic
input
Reset
state
[1]
Type Description