Datasheet
LPC12D27 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 20 September 2011 14 of 46
NXP Semiconductors
LPC12D27
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.
[2] Digital I/O pin; default: pull-up enabled, no hysteresis.
[3] I
2
C-bus pins; 5 V tolerant; open-drain; default: no pull-up/pull-down, no hysteresis.
[4] Digital I/O pin with RESET function; default: pull-up enabled, no hysteresis.
[5] Digital I/O pin with analog function; default: pull-up enabled, no hysteresis.
[6] Digital I/O pin with analog function and WAKEUP function; default: pull-up enabled, no hysteresis.
[7] High-drive digital I/O pin; default: pull-up enabled, no hysteresis.
[8] See Section 7.2.3
.
7. Functional description
7.1 LPC1227 microcontroller
See the LPC122x data sheet for a detailed functional description of the LPC1227
microcontroller.
7.2 LCD driver
See the PCF8576 data sheet for a detailed functional description of the PCF8576D LCD
driver.
7.2.1 General description
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCF8576D communicates via the two-line
bidirectional I
2
C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes). Please refer to PCF8576D data sheet for
electrical data.
BP1 44 - V
LCD
[8]
O LCD backplane output.
BP2 43 - V
LCD
[8]
O LCD backplane output.
BP3 45 - V
LCD
[8]
O LCD backplane output.
LCD_SDA 35 -
[8]
I/O I
2
C-bus serial data input/output.
LCD_SCL 36 -
[8]
I/O I
2
C-bus serial clock input.
SYNC 37 -
[8]
I/O Cascade synchronization input/output.
CLK 38 -
[8]
I/O External clock input/output.
V
DD
39 - - - 1.8 V to 5.5 V power supply: Power supply voltage for the
PCF8576D.
V
SS(LCD)
40 - - - LCD ground.
V
LCD
41 - - - LCD power supply: LCD voltage.
Table 3. LPC12D27 LQFP100 pin description …continued
Symbol Pin Start
logic
input
Reset
state
[1]
Type Description