Datasheet

Product data sheet Rev. 2.2 — 11 March 2014 28 of 77

NXP Semiconductors

LPC11U3x

32-bit ARM Cortex-M0 microcontroller

Power-down mode reduces power consumption compared to Deep-sleep mode at the

expense of longer wake-up times.

7.18.5.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

pin. The LPC11U3x can wake up from Deep power-down mode via the WAKEUP pin.

The LPC11U3x can be prevented from entering Deep power-down mode by setting a lock

bit in the PMU block. Locking out Deep power-down mode enables the application to keep

the watchdog timer or the BOD running at all times.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. Pull the RESET

pin HIGH to prevent it from floating while in

Deep power-down mode.

7.18.6 System control

7.18.6.1 Reset

Reset has four sources on the LPC11U3x: the RESET

pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET

pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

In Deep power-down mode, an external pull-up resistor is required on the RESET

pin.

7.18.6.2 Brownout detection

The LPC11U3x includes up to four levels for monitoring the voltage on the V

pin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a

dedicated status register. Four threshold levels can be selected to cause a forced reset of

the chip.

7.18.6.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details, see the LPC11Uxx user manual.

There are three levels of Code Read Protection: