Datasheet

Product data sheet Rev. 2.2 — 11 March 2014 21 of 77

NXP Semiconductors

LPC11U3x

32-bit ARM Cortex-M0 microcontroller

application notes from NXP (see http://www.LPCware.com.) LPCXpresso, Keil, and IAR

IDEs are supported. I/O Handler library code must be executed from the memory area

0x2000 0000 to 0x2000 07FF. This memory is not available for other use.

For application examples, see Section 11.8 “

I/O Handler software library applications”.

Each I/O Handler library uses a specific subset of I/O Handler pins and in some cases

other pins and peripherals such as the counter/timers.

7.11 USART

The LPC11U3x contains one USART.

The USART includes full modem control, support for synchronous mode, and a smart

card interface. The RS-485/9-bit mode allows both software address detection and

automatic address detection using 9-bit mode.

The USART uses a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.11.1 Features

• Maximum USART data bit rate of 3.125 Mbit/s.

• 16 byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

• Support for synchronous mode.

• Includes smart card interface.

7.12 SSP serial I/O controller

The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. The controller can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave

and from the slave to the master. In practice, often only one of these data flows carries

meaningful data.

7.12.1 Features

• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments

SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation