Datasheet

Product data sheet Rev. 2.3 — 27 March 2014 15 of 74

NXP Semiconductors

LPC11U2x

32-bit ARM Cortex-M0 microcontroller

7.3 SRAM

The LPC11U2x contain a total of 8 kB or 10 kB on-chip static RAM memory.

7.4 On-chip ROM

The on-chip ROM contains the boot loader and the following Application Programming

Interfaces (APIs):

• In-System Programming (ISP) and In-Application Programming (IAP) support for flash

• IAP support for EEPROM

• USB API

• Power profiles for configuring power consumption and PLL settings

• 32-bit integer division routines

7.5 Memory map

The LPC11U2x incorporates several distinct memory regions, shown in the following

figures. Figure 6

shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided

to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is

512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either

type is allocated 16 kB of space. This addressing scheme allows simplifying the address

decoding for each peripheral.