Datasheet
LPC11U1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 47 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
10.4 I/O pins
[1] Applies to standard port pins and RESET pin.
10.5 I
2
C-bus
[1] See the I
2
C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
IH
(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5] C
b
= total capacitance of one bus line in pF.
[6] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
f
.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
Table 14. Dynamic characteristics: I/O pins
[1]
T
amb
=
40
C to +85
C; 3.0 V
V
DD
3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time pin configured as output 3.0 - 5.0 ns
t
f
fall time pin configured as output 2.5 - 5.0 ns
Table 15. Dynamic characteristic: I
2
C-bus pins
[1]
T
amb
=
40
C to +85
C.
[2]
Symbol Parameter Conditions Min Max Unit
f
SCL
SCL clock
frequency
Standard-mode 0 100 kHz
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
t
f
fall time
[4][5][6][7]
of both SDA and SCL
signals
Standard-mode
-300ns
Fast-mode 20 + 0.1 C
b
300 ns
Fast-mode Plus - 120 ns
t
LOW
LOW period of the
SCL clock
Standard-mode 4.7 - s
Fast-mode 1.3 - s
Fast-mode Plus 0.5 - s
t
HIGH
HIGH period of the
SCL clock
Standard-mode 4.0 - s
Fast-mode 0.6 - s
Fast-mode Plus 0.26 - s
t
HD;DAT
data hold time
[3][4][8]
Standard-mode 0 - s
Fast-mode 0 - s
Fast-mode Plus 0 - s
t
SU;DAT
data set-up time
[9][10]
Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns