Datasheet

LPC11U1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 28 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11U1x user manual.
7.16.6.4 APB interface
The APB peripherals are located on one APB bus.
7.16.6.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.16.6.6 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.