Datasheet
LPC11U1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 21 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.11.1 Features
• The I
2
C-interface is an I
2
C-bus compliant interface with open-drain pins. The I
2
C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I
2
C-bus can be used for test and diagnostic purposes.
• The I
2
C-bus controller supports multiple address recognition and a bus monitor mode.
7.12 10-bit ADC
The LPC11U1x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.12.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to V
DD
.
• 10-bit conversion time 2.44 s (up to 400 kSamples/s).
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 General purpose external event counter/timers
The LPC11U1x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.13.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.