Datasheet

LPC11U1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 16 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7. Functional description
7.1 On-chip flash programming memory
The LPC11U1x contain up to 32 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
7.2 SRAM
The LPC11U1x contain a total of 6 kB on-chip static RAM memory.
7.3 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
7.4 Memory map
The LPC11U1x incorporates several distinct memory regions, shown in the following
figures. Figure 5
shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.