Datasheet

LPC11U1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 14 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
[2] 5 V tolerant pad. RESET
functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 31
for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30
).
[4] For parts with bootloader version 7.0, both pins (PIO0_1, PIO0_3) must be pulled LOW to enter UART ISP mode.
[5] I
2
C-bus pins compliant with the I
2
C-bus specification for I
2
C standard mode, I
2
C Fast-mode, and I
2
C Fast-mode Plus. The pin requires
an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30
);
includes high-current output driver.
[7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 30
); includes digital
input glitch filter.
[8] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
[9] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
To assign a peripheral function to a port, program the FUNC bits in the port pin’s IOCON
register with this function. The user must ensure that the assignment of a function to a port
pin is unambiguous. Only the debug functions for JTAG and SWD are selected by default
in their corresponding IOCON registers. All other functions must be programmed in the
IOCON block before they can be used. For details see the LPC11Uxx user manual.
Table 4. Multiplexing of peripheral functions
Peripheral Function Type Default Available on ports
HVQFN33/LQFP48/TFBGA48 LQFP48/TFBGA48 TFBGA48
USART RXD I no PIO0_18 - PIO1_14 PIO1_26 -
TXD O no PIO0_19 - PIO1_13 PIO1_27 -
CTS
Ino PIO0_7 - - - -
RTS
O no PIO0_17 - - - -
DTR
O no PIO1_13 PIO1_19 - - -
DSR
I no - - PIO1_14 PIO1_20 -
DCD
I no PIO1_15 PIO1_21 - -
RI
I no - PIO1_16 PIO1_22 -
SCLK I/O no PIO0_17 PIO1_28 - -
SSP0 SCK0 I/O no PIO0_6 PIO0_10 PIO1_29 -
SSEL0 I/O no PIO0_2 - - - -
MISO0 I/O no PIO0_8 - - - -
MOSI0 I/O no PIO0_9 - - - -
SSP1 SCK1 I/O no PIO1_15 - PIO1_20 - -
SSEL1 I/O no PIO1_19 - PIO1_23 - -
MISO1 I/O no PIO0_22 - PIO1_21 - -
MOSI1 I/O no PIO0_21 - PIO1_22 - -