Datasheet
LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 68 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2] The input resistance of ADC channel 0 is higher than for all other channels.
[3] C
ia
represents the external capacitance on the analog input channel for sampling speeds of 2 Msamples/s.
[4] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width.
See Figure 35
.
[5] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 35
.
[6] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 35
.
[7] The full-scale error voltage or gain error (E
G
) is the difference between the straight-line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See
Figure 35
.
[8] T
amb
= 25 C; maximum sampling frequency f
s
= 2 Msamples/s and analog input capacitance C
ia
=0.1pF.
[9] Input resistance Z
i
is inversely proportional to the sampling frequency and the total input capacity including
C
ia
: Z
i
1 / (f
s
C
i
). See Figure 36 “ADC input impedance”.
Table 22. 12-bit ADC static characteristics
T
amb
=
40
C to +105
C; V
DD
= 2.4 V to 3.6 V; VREFP = V
DDA
; V
SSA
= 0; VREFN = V
SSA
. ADC
calibrated at T = 25
C.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
V
IA
analog input
voltage
[2]
0- V
DDA
V
C
ia
analog input
capacitance
[3]
--0.1pF
f
clk(ADC)
ADC clock
frequency
V
DDA
2.7 V 50 MHz
V
DDA
2.4 V 25 MHz
f
s
sampling
frequency
V
DDA
2.7 V - - 2 Msamples/s
V
DDA
2.4 V - - 1 Msamples/s
E
D
differential
linearity error
[4]
--2.5 LSB
E
L(adj)
integral
non-linearity
[5]
--2.5 LSB
E
O
offset error
[6]
--4.5 LSB
V
err(FS)
full-scale error
voltage
[7]
--0.5 %
Z
i
input
impedance
f
s
= 2 Msamples/s
[8][9]
0.1 - - M