Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 65 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
12.7 USART interface
The maximum USART bit rate for all USARTs is 3.125 Mbit/s in asynchronous mode and
10 Mbit/s in synchronous slave and master mode.
[1] T
cy(clk)
= (main clock cycle time)/(UARTCLKDIV x 2 x (256 x DLM + DLL)). See the LPC11E6x User manual
UM10732.
[1] T
cy(clk)
= U_PCLK/BRGVAL. See the LPC11E6x User manual UM10732.
Table 18. USART dynamic characteristics USART0
T
amb
=  40  C to 105  C; 2.4 V <= V
DD
<= 3.6 V; C
L
= 10 pF. Simulated parameters sampled at the
50 % level of the falling or rising edge; values guaranteed by design.
Symbol Parameter Min Max Unit
T
cy(clk)
clock cycle time
[1]
100 - ns
USART master (in synchronous mode)
t
su(D)
data input set-up time 44 - ns
t
h(D)
data input hold time 0 - ns
t
v(Q)
data output valid time - 10 ns
t
h(Q)
data output hold time 0 - ns
USART slave (in synchronous mode)
t
su(D)
data input set-up time 5 - ns
t
h(D)
data input hold time 20 - ns
t
v(Q)
data output valid time - 40 ns
t
h(Q)
data output hold time 25 - ns
Table 19. USART dynamic characteristics USART1/2/3/4
T
amb
=  40  C to 105  C; 2.4 V <= V
DD
<= 3.6 V; C
L
= 10 pF. Simulated parameters sampled at the
50 % level of the falling or rising edge; values guaranteed by design.
Symbol Parameter Min Max Unit
T
cy(clk)
clock cycle time
[1]
100 - ns
USART master (in synchronous mode)
t
su(D)
data input set-up time 44 - ns
t
h(D)
data input hold time 0 - ns
t
v(Q)
data output valid time - 10 ns
t
h(Q)
data output hold time 0 - ns
USART slave (in synchronous mode)
t
su(D)
data input set-up time 5 - ns
t
h(D)
data input hold time 0 - ns
t
v(Q)
data output valid time - 40 ns
t
h(Q)
data output hold time 20 - ns