Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 63 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
12.6 SSP interface
[1] T
cy(clk)
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the
main clock frequency f
main
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] T
amb
= 40 C to 105 C; 2.4 V  V
DD
 3.6 V.
[3] T
cy(clk)
= 12  T
cy(PCLK)
.
[4] T
amb
= 25 C; for normal voltage supply range: V
DD
= 3.3 V.
Table 17. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
SPI master (in SPI mode)
T
cy(clk)
clock cycle time full-duplex mode
[1]
50 - - ns
when only transmitting
[1]
40 ns
t
DS
data set-up time in SPI mode
[2]
15 - - ns
t
DH
data hold time in SPI mode
[2]
0-- ns
t
v(Q)
data output valid time in SPI mode
[2]
--10 ns
t
h(Q)
data output hold time in SPI mode
[2]
0-- ns
SPI slave (in SPI mode)
T
cy(PCLK)
PCLK cycle time 20 - - ns
t
DS
data set-up time in SPI mode
[3][4]
0-- ns
t
DH
data hold time in SPI mode
[3][4]
3  T
cy(PCLK)
+ 4 - - ns
t
v(Q)
data output valid time in SPI mode
[3][4]
--3  T
cy(PCLK)
+ 11 ns
t
h(Q)
data output hold time in SPI mode
[3][4]
--2  T
cy(PCLK)
+ 5 ns
Fig 32. SSP master timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID
DATA VALID
MOSI
MISO
t
DS
t
DH
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
t
v(Q)
CPHA = 1
CPHA = 0
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