Datasheet
LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 53 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
The power profiles optimize the chip performance for power consumption or core
efficiency by controlling the flash access and core power. As shown in Figure 21
and
Figure 22
, different power modes result in different CoreMark scores reflecting the
trade-off of efficiency and power consumption. In CPU and efficiency modes, the power
profiles aim to keep the core efficiency at a maximum for the given system frequency.
Depending on optimal flash access parameters that change with frequency, the CoreMark
score and also the power consumption change. Since the compiled code for CoreMark
testing runs out of flash memory, the CoreMark score depends on the compiler version.
11.3 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code accessing the peripheral is executed except for the ADC. Measured
on a typical sample at T
amb
=25 C. Unless noted otherwise, the system oscillator and
PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
Table 9. Power consumption for individual analog and digital blocks
Peripheral Typical supply current in mA Notes
n/a 12 MHz 48 MHz
IRC 0.24 - - System oscillator running; PLL off; independent
of main clock frequency.
System oscillator at 12 MHz 0.28 - - IRC running; PLL off; independent of main clock
frequency.
WatchDog oscillator at
600 kHz/2
0 - - System oscillator running; PLL off; independent
of main clock frequency.
BOD 0.05 - - Independent of main clock frequency.
System PLL 0.25 - - -
CLKOUT - 0.25 0.89 System PLL is source of CLKOUT.
ROM - 0.09 0.37 -
FLASHREG - 0.17 0.66 -
FLASHARRAY - 0.13 0.52 -
SRAM1 - 0.15 0.59 -
SRAM2 - 0.14 0.56 -
GPIO + pin interrupt/pattern
match
- 0.18 0.69 GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
IOCON - 0.08 0.30 -
SCTimer0/PWM +
SCTimer1/PWM
- 0.29 1.1 -
CT16B0 - 0.05 0.17 -
CT16B1 - 0.04 0.16 -
CT32B0 - 0.04 0.13 -
CT32B1 - 0.03 0.13 -
RTC - 0.02 0.10 -