Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 5 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
6. Block diagram
Gray-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or have DMA request lines.
(1) Available on LQFP100 packages only.
Fig 3. LPC11E6x block diagram
ARM
CORTEX-M0+
SWD TEST/DEBUG
INTERFACE
SYSTICK
NVIC
PROCESSOR CORE
PRECISION
IRC
SYSTEM
PLL
WATCHDOG
OSCILLATOR
SYSTEM
OSCILLATOR
RTC
OSCILLATOR
GENERAL PURPOSE
BACKUP REGISTERS
CLOCK
GENERATION
256/128/64 KB FLASH
ROM
36/20/12 KB SRAM
4 KB EEPROM
TEMPERATURE SENSOR
MEMORY
PORT0/1/2
GINT0/1
PINTSEL
PINT/
PATTERN MATCH
SCTIMER0/
PWM
HS GPIO+
SCTIMER1/
PWM
DMA TRIGGER
PWM/TIMER SUBSYSTEM
USART0 USART1
USART3 USART4
(1)
FM+ I2C0
USART2
SSP1
SSP0
I2C1
SYSCON IOCON PMU CRC FLASH CTRL EEPROM CTRL
SYSTEM/MEMORY CONTROL
CT16B0 CT32B0
CT16B1 CT32B1
WWDTRTC
ALWAYS-ON POWER DOMAIN
SYSTEM TIMER
SERIAL PERIPHERALS
12-bit ADC0
TRIGGER MUX
ANALOG PERIPHERALS
AHB MULTILAYER
MATRIX
AHB/APB BRIDGES
DMA
LPC11E6x
pads
n
IOCON
aaa-011045