Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 49 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
Conditions: V
DD
= 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F; all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz - 6 MHz: IRC enabled; PLL disabled.
12 MHz: IRC enabled; PLL disabled.
24 MHz to 50 MHz: IRC disabled; PLL enabled; sysosc enabled.
Fig 15. Active mode: Typical supply current I
DD
versus temperature
Conditions: V
DD
= 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F) all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz - 6 MHz: IRC enabled; PLL disabled.
12 MHz: IRC enabled; PLL disabled.
24 MHz to 48 MHz: IRC disabled; PLL enabled; sysosc enabled.
Fig 16. Sleep mode: Typical supply current I
DD
versus temperature for different system
clock frequencies
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