Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 40 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC11U6x/Ex user manual.
8.26 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is
configured to support up to four breakpoints and two watch points.
The RESET
pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET
= HIGH). The ARM SWD debug port is disabled while the
LPC11E6x is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET
pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET
pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST
pin to enable the
SWD debug mode, and release the RESET
pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.