Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 38 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
The LPC11E6x can wake up from Power-down mode via reset, selected GPIO pins, a
watchdog timer interrupt, an RTC interrupt, or any interrupts that the USART1 to USART4
interfaces can create in Power-down mode. The USART wake-up requires the 32 kHz
mode, the synchronous mode, or the CTS interrupt to be set up.
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
8.24.7.5 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pin and the always-on RTC power domain. The LPC11E6x can wake up from Deep
power-down mode via the WAKEUP pin or a wake-up signal generated by the RTC
interrupt.
The LPC11E6x can be blocked from entering Deep power-down mode by setting a lock bit
in the PMU block. Blocking the Deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
If the WAKEUP pin is used in the application, an external pull-up resistor is required on
the WAKEUP pin to hold it HIGH while the part is in deep power-down mode. To wake up
from deep power-down mode, pull the WAKEUP pin LOW. In addition, pull the RESET
pin
HIGH to prevent it from floating while in Deep power-down mode.
8.25 System control
8.25.1 Reset
Reset has four sources on the LPC11E6x: the RESET pin, the WatchDog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET
pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values. The internal reset
status is reflected on the RSTOUT
pin.
In Deep power-down mode, an external pull-up resistor is required on the RESET
pin.
The RESET
pin is operational in active, sleep, deep-sleep, and power-down modes if the
RESET
function is selected in the IOCON register for pin PIO0_0 (this is the default). A
LOW-going pulse as short as 50 ns executes the reset and also wakes up the part if in
sleep, deep-sleep or power-down mode. The RESET
pin is not functional in Deep
power-down mode.