Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 34 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
8.24 Clocking and power control
8.24.1 Clock generation
8.24.2 Power domains
The LPC11E6x provide two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the RTC and the backup registers.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(V
DD
) is used to operate the RTC whenever V
DD
is present. Therefore, there is no power
drain from the RTC battery when V
DD
is available and V
DD
 VBAT + 0.3 V.
Fig 10. Clock generation
watchdog oscillator
IRC oscillator
SYSTEM CLOCK
DIVIDER
SYSAHBCLKCTRL
(AHB clock enable)
CPU,
system control,
PMU
memories,
peripheral clocks
SSP0 PERIPHERAL
CLOCK DIVIDER
SSP0
SSP1 PERIPHERAL
CLOCK DIVIDER
SSP1
USART0 PERIPHERAL
CLOCK DIVIDER
USART0
WDT
WDCLKSEL
(WDT clock select)
CLKOUTSEL
(CLKOUT clock select)
watchdog oscillator
IRC oscillator
system oscillator
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
RTC
oscillator,
32 kHz
output
RTCOSCCTRL
(RTC osc enable)
system clock
SYSTEM PLL
IRC
system
oscillator
watchdog oscillator
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
(system PLL clock select)
main
clock
IRC
n
CLOCK DIVIDER
FRGCLKDIV
USART1
USART2
USART3
USART4
IOCONCLKDIV
CLOCK DIVIDER
IOCON
glitch filter
7
FRACTIONAL RATE
GENERATOR
aaa-011053