Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 28 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
• 4-bit to 16-bit frame
• DMA support
8.17 I
2
C-bus serial I/O controller
The LPC11E6x contain two I
2
C-bus controllers.
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and can be
controlled by more than one bus master connected to it.
8.17.1 Features
• One I
2
C-interface (I2C0) is an I
2
C-bus compliant interface with open-drain pins. The
I
2
C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• One I
2
C-interface (I2C1) uses standard digital pins. The I
2
C-bus interface supports bit
rates up to 400 kbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I
2
C-bus can be used for test and diagnostic purposes.
• The I
2
C-bus controller supports multiple address recognition and a bus monitor mode.
8.18 Timer/PWM subsystem
Four standard timers and two state configurable timers can be combined to create
multiple PWM outputs using the match outputs and the match registers for each timer.
Each timer can create multiple PWM outputs with its own time base.