Datasheet

Product data sheet Rev. 1.2 — 21 May 2014 27 of 89

NXP Semiconductors

LPC11E6x

32-bit ARM Cortex-M0+ microcontroller

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software-address compare feature.

(RS-485 possible with software address detection and transceiver direction control.)

• RS-485 transceiver output enable.

• Autobaud mode for automatic baud rate detection

• Parity generation and checking: odd, even, or none.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Loopback mode for testing of data and flow control.

• In synchronous slave mode, wakes up the part from deep-sleep and power-down

modes.

• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC

oscillator as the UART clock. This mode can be used while the device is in

Deep-sleep or Power-down mode and can wake up the device when a character is

received.

• USART transmit and receive functions work with the system DMA controller.

8.16 SSP serial I/O controller (SSP0/1)

The SSP controllers operate on an SSP, 4-wire SSI, or Microwire bus. The controller can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave

and from the slave to the master. In practice, often only one direction carries meaningful

data.

8.16.1 Features

• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments

SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive