Datasheet

Product data sheet Rev. 1.2 — 21 May 2014 22 of 89

NXP Semiconductors

LPC11E6x

32-bit ARM Cortex-M0+ microcontroller

8.8.1 Features

• Controls system exceptions and peripheral interrupts.

• In the LPC11E6x, the NVIC supports vectored interrupts for each of the peripherals

and the eight pin interrupts. The following peripheral interrupts are ORed to contribute

to one interrupt in the NVIC:

– USART1, USART4

– USART2, USART3

– SCTimer0/PWM, SCTimer1/PWM

– BOD, WWDT

– ADC end-of-sequence A interrupt, threshold crossing interrupt

– ADC end-of-sequence B interrupt, overrun interrupt

– Flash, EEPROM

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation.

8.8.2 Interrupt sources

Each peripheral device has at least one interrupt line connected to the NVIC but can have

several interrupt flags. Individual interrupt flags can also represent more than one interrupt

source.

8.9 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Connect peripherals to the appropriate pins before activating the peripheral and before

enabling any related interrupt.

Enabling an analog function disables the digital pad. However, the internal pull-up and

pull-down resistors as well as the pin hysteresis must be disabled to obtain an accurate

reading of the analog input.

8.9.1 Features

• Programmable pin function.

• Programmable pull-up, pull-down, or repeater mode.

• All pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V

= 3.3 V) if their

pull-up resistor is enabled.

• Programmable pseudo open-drain mode.

• Programmable (on/off) 10 ns glitch filter on pins PIO0_22, PIO0_23, PIO0_11 to

PIO0_16, PIO1_3, PIO1_9, PIO1_22, and PIO1_29. The glitch filter is turned on by

default.

• Programmable hysteresis.

• Programmable input inverter.