Manualshelf

Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 32-Bit 50 MHz I/O number 36
11121314151617181920
LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 20 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
8.3 On-chip flash programming memory
The LPC11E6x contain up to 256 KB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip bootloader software.
The flash memory is divided into 24 x 4 KB and 5 x 32 KB sectors. Individual pages of
256 byte each can be erased using the IAP erase page command.
8.4 EEPROM
The LPC11E6x contain 4 KB of on-chip byte-erasable and byte-programmable EEPROM
data memory. The EEPROM can be programmed using In-Application Programming (IAP)
via the on-chip bootloader software.
8.5 SRAM
The LPC11E6x contain a total of up to 36 KB on-chip static RAM memory. The main
SRAM block contains either 8 KB, 16 KB. or 32 KB of main SRAM0. Two additional SRAM
blocks of 2 KB (SRAM1 and SRAM2) are located in separate areas of the memory map.
See Figure 8
.
8.6 On-chip ROM
The on-chip ROM contains the bootloader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
• IAP support for EEPROM
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
• APIs to use the following peripherals:
– I2C
– USART0 and USART1/2/3/4
– DMA
8.7 Memory mapping
The LPC11E6x incorporates several distinct memory regions, shown in the following
figures. Figure 8
shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided
to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is
512 KB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 KB of space. This addressing scheme allows simplifying the address
decoding for each peripheral.