Datasheet

LPC11E6X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1.2 — 21 May 2014 19 of 89
NXP Semiconductors
LPC11E6x
32-bit ARM Cortex-M0+ microcontroller
Fig 7. AHB multilayer matrix
ARM
CORTEX-M0+
TEST/DEBUG
INTERFACE
DMA
AHB-TO-APB
BRIDGE
EEPROM
HS GPIO
slaves
SRAM1
System
bus
masters
FLASH
ROM
AHB MULTILAYER MATRIX
= master-slave connection
WWDT
USART0
CT32B0
I2C0
FLASHCTRL SSP0
CT32B1 DMA TRIGMUX
PMU
I2C1ADC
IOCON
RTC
GROUP0
GROUP1
USART1
SSP1
USART4
SYSCON
MAIN SRAM0
SRAM2
SCTIMER0/PWM
SCTIMER1/PWM
PINT/PATTERN MATCH
CRC
DMA REGISTERS
CT16B0 CT16B1
USART2
USART3
USART2
aaa-011051