Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 32-Bit 50 MHz I/O number 36

1. General description

The LPC11E6x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 50 MHz. The LPC11E6x support up to 256 KB of flash memory,

a 4 KB EEPROM, and 36 KB of SRAM.

The ARM Cortex-M0+ is an easy-to-use, energy-efficient core using a two-stage pipeline

and fast single-cycle I/O access.

The peripheral complement of the LPC11E6x includes a DMA controller, a CRC engine,

two I

C-bus interfaces, up to five USARTs, two SSP interfaces, PWM/timer subsystem

with six configurable multi-purpose timers, a Real-Time Clock, one 12-bit ADC,

temperature sensor, function-configurable I/O ports, and up to 80 general-purpose I/O

pins.

For additional documentation related to the LPC11E6x parts, see Section 18

“References”.

2. Features and benefits

 System:

 ARM Cortex-M0+ processor (version r0p1), running at frequencies of up to 50 MHz

with single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 AHB Multilayer matrix.

 System tick timer.

 Serial Wire Debug (SWD) and JTAG boundary scan modes supported.

 Micro Trace Buffer (MTB) supported.

 Memory:

 Up to 256 KB on-chip flash programming memory with page erase.

 Up to 32 KB main SRAM.

 Up to two additional SRAM blocks of 2 KB each.

 Up to 4 KB EEPROM.

 ROM API support:

 Boot loader.

 USART drivers.

 I2C drivers.

 DMA drivers.

 Power profiles.

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

LPC11E6x

32-bit ARM Cortex-M0+ microcontroller; up to 256 kB flash

and 36 kB SRAM; 4 kB EEPROM; 12-bit ADC

Rev. 1.2 — 21 May 2014 Product data sheet

Summary of content (89 pages)

PAGE 1
LPC11E6x 32-bit ARM Cortex-M0+ microcontroller; up to 256 kB flash and 36 kB SRAM; 4 kB EEPROM; 12-bit ADC Rev. 1.2 — 21 May 2014 Product data sheet 1. General description The LPC11E6x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 50 MHz. The LPC11E6x support up to 256 KB of flash memory, a 4 KB EEPROM, and 36 KB of SRAM. The ARM Cortex-M0+ is an easy-to-use, energy-efficient core using a two-stage pipeline and fast single-cycle I/O access.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller         LPC11E6X Product data sheet  32-bit integer division routines. Digital peripherals:  Simple DMA engine with 16 channels and programmable input triggers.  High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 80 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and programmable glitch filter and digital filter.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller       Power-On Reset (POR).  Brownout detect. Unique device serial number for identification. Single power supply (2.4 V to 3.6 V). Separate VBAT supply for RTC. Operating temperature range -40 °C to 105 °C. Available as LQFP48, LQFP64, and LQFP100 packages. 3. Applications  Three-phase e-meter  GPS tracker  Gaming accessories  Car radio  Medical monitor  PC peripherals 4. Ordering information Table 1.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 5. Marking n n Terminal 1 index area 1 Terminal 1 index area aaa-011231 Fig 1. LQFP64/100 package marking Fig 2. 1 aaa-011232 LQFP48 package marking 5.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 6.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 25 PIO1_21 26 PIO0_8 27 PIO0_9 28 SWCLK/PIO0_10 29 PIO0_22 30 TDI/PIO0_11 31 TMS/PIO0_12 32 TDO/PIO0_13 33 TRST/PIO0_14 34 VREFP 35 VREFN 36 PIO1_13 7.
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LPC11E6x NXP Semiconductors 33 PIO2_18 34 VDD 35 PIO1_21 36 PIO2_19 37 PIO0_8 38 PIO0_9 39 SWCLK/PIO0_10 40 PIO0_22 41 PIO1_29 42 TDI/PIO0_11 43 TMS/PIO0_12 44 PIO1_30 45 TDO/PIO0_13 46 TRST/PIO0_14 47 VREFP 48 VREFN 32-bit ARM Cortex-M0+ microcontroller PIO1_13 49 32 PIO2_15 SWDIO/PIIO0_15 50 31 PIO1_28 PIO0_16/WAKEUP 51 30 PIO0_7 PIO0_23 52 29 PIO0_6 VDDA 53 28 PIO1_24 VSSA 54 27 PIO2_4 PIO1_9 55 26 PIO2_7 PIO0_17 56 25 PIO2_6 LPC11E6XJBD64 VSS 57 23 PIO1_23 VDD 59 2
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7.2 Pin description LQFP100 RESET/PIO0_0 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions. 3 4 8 [8] Reset Type state[1] Description of pin functions I; PU RESET — External reset input with 20 ns glitch filter.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO0_8 PIO0_9 SWCLK/PIO0_10 TDI/PIO0_11 TMS/PIO0_12 TDO/PIO0_13 LPC11E6X Product data sheet LQFP100 PIO0_7 24 30 45 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller SWDIO/PIO0_15 PIO0_16/WAKEUP PIO0_17 PIO0_18 PIO0_19 PIO0_20 PIO0_21 LPC11E6X Product data sheet LQFP100 TRST/PIO0_14 33 46 69 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO0_23 PIO1_0 PIO1_1 PIO1_2 PIO1_3 PIO1_4 PIO1_5 PIO1_6 LPC11E6X Product data sheet LQFP100 PIO0_22 29 40 62 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO1_8 PIO1_9 PIO1_10 PIO1_11 PIO1_12 PIO1_13 PIO1_14 PIO1_15 LPC11E6X Product data sheet LQFP100 PIO1_7 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO1_17 PIO1_18 PIO1_19 PIO1_20 PIO1_21 PIO1_22 PIO1_23 PIO1_24 LPC11E6X Product data sheet LQFP100 PIO1_16 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO1_26 PIO1_27 PIO1_28 PIO1_29 PIO1_30 LQFP100 PIO1_25 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions. - - 100 - - - - - 15 17 31 41 44 20 22 46 63 67 [6] [6] [6] [6] [3] [6] Reset Type state[1] Description of pin functions I; PU IO PIO1_25 — General-purpose digital input/output pin.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO2_3 PIO2_4 PIO2_5 PIO2_6 PIO2_7 PIO2_8 PIO2_9 PIO2_10 PIO2_11 PIO2_12 PIO2_13 PIO2_14 LPC11E6X Product data sheet LQFP100 PIO2_2 12 16 21 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO2_16 PIO2_17 PIO2_18 PIO2_19 PIO2_20 PIO2_21 LQFP100 PIO2_15 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART4 pin functions. - 32 49 - 33 36 - [6] 50 [6] 51 [6] 52 [6] 57 [6] Reset Type state[1] Description of pin functions I; PU IO PIO2_15 — General-purpose digital input/output pin. I SCT1_IN3 — SCTimer1/PWM input 3.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [1] Pin state at reset for default function: I = Input; O = Output; AI = Analog Input; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption. [2] Special analog pad. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8. Functional description 8.1 ARM Cortex-M0+ core The ARM Cortex-M0+ core runs at an operating frequency of up to 50 MHz using a two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller TEST/DEBUG INTERFACE ARM CORTEX-M0+ DMA masters System bus slaves FLASH MAIN SRAM0 SRAM2 SRAM1 ROM EEPROM SCTIMER0/PWM SCTIMER1/PWM HS GPIO PINT/PATTERN MATCH CRC DMA REGISTERS AHB-TO-APB BRIDGE CT32B0 PMU USART0 WWDT I2C0 AHB MULTILAYER MATRIX CT32B1 ADC FLASHCTRL USART4 SSP1 USART2 I2C1 SSP0 RTC IOCON GROUP0 USART3 CT16B0 CT16B1 DMA TRIGMUX SYSCON GROUP1 USART1 USART2 = master-slave connection aaa-011051
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.3 On-chip flash programming memory The LPC11E6x contain up to 256 KB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip bootloader software. The flash memory is divided into 24 x 4 KB and 5 x 32 KB sectors. Individual pages of 256 byte each can be erased using the IAP erase page command. 8.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 4 GB LPC11E6x 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved 0xA000 8000 GPIO PINT 0xA000 4000 GPIO 0xA000 0000 APB peripherals reserved 0x5001 0000 SCTIMER1/PWM 0x5000 E000 SCTIMER0/PWM 0x4007 8000 0x5000 C000 reserved 0x5000 8000 DMA 0x5000 4000 CRC 0x4008 4000 APB peripherals USART2 27 USART1 24 GPIO GROUP1 interrupt 23 GPIO GROUP0 interrupt 22 SSP1 0x2000 4000 reserved 0x2000 0800
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.8.1 Features • Controls system exceptions and peripheral interrupts. • In the LPC11E6x, the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Digital filter with programmable filter constant on all pins. The minimum filter constant is 1/50 MHz = 20 ns. 8.9.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LPC11E6x use accelerated GPIO functions: • GPIO registers are on the ARM Cortex-M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 25 MHz. • An entire port value can be written in one instruction. • Mask, set, and clear operations are supported for the entire port. 8.10.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.12 GPIO group interrupts The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts. For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO grouped interrupt registers determine which pins are enabled to generate interrupts and the active polarities of each of those inputs.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.14 USART0 Remark: The LPC11E6x contains two distinctive types of UART interfaces: USART0 is software-compatible with the USART interface on the LPC11E1x/3x parts. USART1 to USART4 use a different register interface. The USART0 includes full modem control, support for synchronous mode, and a smart card interface. The RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software-address compare feature. (RS-485 possible with software address detection and transceiver direction control.) • • • • • RS-485 transceiver output enable.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • 4-bit to 16-bit frame • DMA support 8.17 I2C-bus serial I/O controller The LPC11E6x contain two I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Peripheral Pin functions available for PWM Match registers used LQFP100 LQFP64 LQFP48 LQFP48 PWM outputs LQFP64 PWM resources LQFP100 Table 4.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.18.1 State Configurable Timers (SCTimer0/PWM and SCTimer1/PWM) The state configurable timer can create timed output signals such as PWM outputs triggered by programmable events. Combinations of events can be used to define timer states. The SCTimer/PWM can control the timer operations, capture inputs, change states, and toggle outputs triggered only by events entirely without CPU intervention.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller – Each event can be assigned to one or more states. – State variable allows sequencing across multiple counter cycles. • SCTimer match outputs (ORed with the general-purpose timer match outputs) serve as ADC hardware trigger inputs. 8.18.2 General purpose external event counter/timers (CT32B0/1 and CT16B0/1) The LPC11E6x includes two 32-bit counter/timers and two 16-bit counter/timers.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.20.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time before watchdog time-out. • Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is required to disable the WWDT.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Optional automatic high/low threshold comparison and zero-crossing detection. • Power-down mode and low-power operating mode. • Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage level). • Burst conversion mode for single or multiple inputs. 8.23 Temperature sensor The temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a CTAT voltage (Complement To Absolute Temperature).
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.24 Clocking and power control 8.24.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LPC11E6x to I/O pads to core VSS REGULATOR to memories, peripherals, oscillators, PLL VDD MAIN POWER DOMAIN WAKEUP ULTRA LOW-POWER REGULATOR VBAT WAKE-UP CONTROL BACKUP REGISTERS RTCXIN 32 kHz OSCILLATOR RTCXOUT REAL-TIME CLOCK ALWAYS-ON/RTC POWER DOMAIN ADC TEMP SENSE VDDA VDD ADC POWER DOMAIN VSSA aaa-011054 Fig 11. Power distribution 8.24.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. The system oscillator has a wake-up time of approximately 500 μs. 8.24.3.3 WatchDog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 8.24.7.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The LPC11E6x can wake up from Power-down mode via reset, selected GPIO pins, a watchdog timer interrupt, an RTC interrupt, or any interrupts that the USART1 to USART4 interfaces can create in Power-down mode. The USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS interrupt to be set up. Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 8.24.7.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9'' 9'' 9'' 5SX UHVHW (6' QV 5& */,7&+ ),/7(5 3,1 (6' 966 DDD Fig 12. RESET pin configuration 8.25.2 Brownout detection The LPC11E6x includes two levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details, see the LPC11U6x/Ex user manual. 8.26 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD supply voltage VDDA analog supply voltage Vref reference voltage VBAT battery supply voltage Conditions [2] on pin VREFP input voltage VI 5 V tolerant I/O pins; only valid when the VDD(IO) supply voltage is present Max Unit 0.5 4.6 V 0.5 4.6 V 0.5 4.6 V 0.5 4.6 V [3][4] 0.
PAGE 42
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [6] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
PAGE 43
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 7. Thermal resistance value (C/W): ±15 % Symbol Parameter Typ Unit jc thermal resistance junction-to-case Conditions 18 C/W jb thermal resistance junction-to-board 23 C/W 0 m/s 49 C/W 1 m/s 44 C/W 2.5 m/s 41 C/W 0 m/s 66 C/W 1 m/s 55 C/W LQFP100 ja thermal resistance junction-to-ambient JEDEC (4.5 in  4 in) 8-layer (4.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions IDD supply current Sleep mode; IDD supply current system clock = 12 MHz; default mode; VDD = 3.3 V [2][3][4] system clock = 12 MHz; low-current mode; VDD = 3.3 V [2][3][4] system clock = 50 MHz; default mode; VDD = 3.3 V [2][3][9] system clock = 50 MHz; low-current mode; VDD = 3.
PAGE 45
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Typ[1] Max Symbol Parameter Conditions Min Unit VOH HIGH-level output voltage IOH = 4 mA VDD  0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 4 - - mA IOL LOW-level output current VOL = 0.
PAGE 46
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Ipd Parameter pull-down current pull-up current Ipu Min Typ[1] Max Unit VI = 5 V [16] 10 50 150 A VI = 0 V [16] 10 50 85 A 0 0 0 A V Conditions VDD < VI < 5 V I2C-bus pins (PIO0_4 and PIO0_5); see Figure 13 VIH HIGH-level input voltage 0.7 VDD - - VIL LOW-level input voltage - - 0.
PAGE 47
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 13. [17] To VSS. [18] The parameter values specified are simulated and absolute values. [19] The input voltage of the RTC oscillator is limited as follows: Vi(rtcx), Vo(rtcx) < max(VBAT, VDD).
PAGE 48
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.1 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW.
PAGE 49
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' P$ 0+] 0+] 0+] 0+] 0+] 0+] WHPSHUDWXUH & Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F; all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled.
PAGE 50
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' ȝ$ 9 9 9 9 9 7 & Conditions: BOD disabled; all oscillators and analog blocks disabled Fig 17. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD DDD ,'' ȝ$ 7 & Conditions: BOD disabled; all oscillators and analog blocks disabled; VDD = 2.4 V to 3.6 V.
PAGE 51
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' ȝ$ 9 9 9 9 9 7 & Conditions: RTC running; VBAT = 0 V Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD DDD ,%$7 ȝ$ 7 & Conditions: RTC not running; VBAT = 3.0 V; VDD floating. Fig 20.
PAGE 52
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.2 CoreMark data aaa-011173 2.5 CM (((iterations/s)/MHz)) 2.25 cpu performance efficiency default/low-current 2 aaa-011174 2.5 CM (((iterations/s)/MHz)) 2.25 cpu performance efficiency default/low-current 2 1.75 1.75 1.5 1.5 1.25 1.25 1 1 0 10 20 30 40 system clock frequency (MHz) 50 Measured with Keil uVision v.4.72. 0 10 20 30 40 system clock frequency (MHz) 50 Measured with Keil uVision v.4.60.
PAGE 53
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The power profiles optimize the chip performance for power consumption or core efficiency by controlling the flash access and core power. As shown in Figure 21 and Figure 22, different power modes result in different CoreMark scores reflecting the trade-off of efficiency and power consumption. In CPU and efficiency modes, the power profiles aim to keep the core efficiency at a maximum for the given system frequency.
PAGE 54
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 9. Power consumption for individual analog and digital blocks …continued Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz WWDT - 0.05 0.17 Main clock selected as clock source for the WDT. I2C0 - 0.05 0.22 - I2C1 - 0.05 0.18 - SSP0 - 0.15 0.59 - SSP1 - 0.15 0.58 - USART0 - 0.31 1.19 - USART1 - 0.12 0.50 - USART2 - 0.13 0.49 - USART3 + USART4 - 0.21 0.81 - ADC0 - 2.
PAGE 55
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.4 Electrical pin characteristics DDD 92+ 9 9 & 9 & 9 & 9 & ,2+ P$ 9 & & 9 & & 9 & & 9 & & DDD 92+ 9 Conditions: VDD = 2.4 V; ON pin PIO0_7 and PIO1_31. ,2+ P$ Conditions: VDD = 3.3 V; ON pin PIO0_7 and PIO1_31. Fig 23.
PAGE 56
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,2/ P$ DDD ,2/ P$ 9 & & 9 & & 9 & & 9 & & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 92/ 9 Conditions: VDD = 2.4 V; standard port pins and high-drive pins PIO0_7 and PIO1_31. 92/ 9 Conditions: VDD = 3.
PAGE 57
LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,38 ȝ$ DDD ,38 ȝ$ 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9, 9 Conditions: VDD = 2.4 V; standard port pins. 9, 9 Conditions: VDD = 3.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12. Dynamic characteristics 12.1 Flash/EEPROM memory Table 10. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. W&+&/ W&+&; W&/&+ W&/&; 7F\ FON DDD Fig 29. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 12.3 Internal oscillators Table 13. Dynamic characteristics: IRC Tamb = 40 C to +105 C; 2.7 V  VDD  3.6 V[1].
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 14. Dynamic characteristics: WatchDog oscillator Symbol Parameter Conditions fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register Min Typ[1] Max Unit [2][3] - 9.4 - kHz [2][3] - 2300 - kHz [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 16. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller WI 6'$ W68 '$7 W+' '$7 WI 6&/ W9' '$7 W+,*+ W/2: 6 I6&/ DDD Fig 31. I2C-bus pins clock timing LPC11E6X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 21 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.6 SSP interface Table 17.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 33. SSP slave timing in SPI mode LPC11E6X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 21 May 2014 © NXP Semiconductors N.V. 2014.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.7 USART interface The maximum USART bit rate for all USARTs is 3.125 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous slave and master mode. Table 18. USART dynamic characteristics USART0 Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF. Simulated parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7F\ FON 8QB6&/. &/.32/ 8QB6&/. &/.32/ WY 4 WK 4 67$57 7;' %,7 %,7 WVX ' WK ' 67$57 5;' %,7 %,7 DDD Fig 34. USART timing 12.8 SCTimer/PWM output timing To estimate the skew between different outputs, compare the worst case to worst case (or best case to best case) values of individual pins. Table 20. SCTimer/PWM output dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13. Characteristics of analog peripherals Table 21. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 2 Min Typ Max Unit assertion - 2.54 - V de-assertion - 2.68 - V assertion - 2.82 - V de-assertion - 2.93 - V assertion - 2.34 - V de-assertion - 2.49 - V assertion - 2.62 - V de-assertion - 2.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 22. 12-bit ADC static characteristics Tamb = 40 C to +105 C; VDD = 2.4 V to 3.6 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA. ADC calibrated at T = 25C. Symbol Parameter Conditions Min Typ Max Unit [1] VIA analog input voltage [2] 0 - VDDA V Cia analog input capacitance [3] - - 0.1 pF fclk(ADC) ADC clock frequency VDDA 2.7 V 50 MHz VDDA 2.4 V 25 MHz sampling frequency VDDA 2.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller ADC R1 = 0.25 kΩ...2.5 kΩ ADCn_0 Cio Rsw = 5 Ω...25 Ω ADCn_[1:11] DAC CDAC Cio Cia aaa-011748 Fig 36. ADC input impedance Table 23. Temperature sensor static and dynamic characteristics VDDA = 2.4 V to 3.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD 92 P9 WHPSHUDWXUH & VDDA = 3.3 V; measured on a typical silicon sample. Fig 37. Typical LLS fit of the temperature sensor output voltage 14. Application information 14.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [3] WatchDog oscillator disabled, Brown-Out Detect (BOD) disabled. [4] Wake-up from deep power-down causes the part to go through entire reset process. The wake-up time measured is the time between when a wake-up pin is triggered to wake up the device from the low-power modes and when a GPIO output pin is set in the reset handler. 14.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LPC1xxx L XTALIN XTALOUT CL = CP XTAL RS CX2 CX1 002aaf424 Fig 39. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 26.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Smaller values of Cx1 and Cx2 should be chosen according to the increase in parasitics of the PCB layout. 14.5 RTC oscillator component selection The 32 kHz crystal must be connected to the part via the RTCXIN and RTCXOUT pins as shown in Figure 40. If the RTC is not used, the RTCXIN pin can be grounded.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 3.3 V 3.3 V SWD connector ~10 kΩ - 100 kΩ Note 6 SWDIO/PIO0_15 1 2 3 4 5 6 n.c. 7 8 n.c. 9 10 SWCLK/PIO0_10 ~10 kΩ - 100 kΩ PIO2_0/XTALIN C1 n.c. Note 1 DGND C2 PIO2_1/XTALOUT RESET/PIO0_0 DGND RTCXIN Note 2 C3 VSS C4 RTCXOUT DGND DGND DGND 3.3 V 0.01 μF 0.1 μF AGND Note 3 VDD (2 to 5 pins) VSSA LPC11E6x DGND PIO0_1 Note 4 3.3 V VDDA ISP select pins PIO0_3 10 μF 0.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14.7 Termination of unused pins Table 28 shows how to terminate pins that are not used in the application. In many cases, unused pins should be connected externally or configured correctly by software to minimize the overall power consumption of the part. Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull-up disabled.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14.8 Pin states in different power modes Table 29. Pin states in different power modes Pin Active Sleep Deep-sleep/Powerdown PIOn_m pins (not As configured in the IOCON[1]. Default: internal pull-up enabled. I2C) Deep power-down Floating. PIO0_4/PIO0_5 (open-drain I2C-bus pins) As configured in the IOCON[1]. Floating. RESET Reset function enabled. Default: input, internal pull-up enabled.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 15. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 16. Soldering Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 45.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 46.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.550 sot407-1 Fig 47.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 17. Abbreviations Table 30. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port UART Universal Asynchronous Receiver/Transmitter 18.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 19. Revision history Table 31. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11E6X v.1.2 20140521 Product data sheet - Modifications: LPC11E6X v.1.1 Modifications: LPC11E6X v.1 LPC11E6X Product data sheet LPC11E6X v.1.1 • Parts added: LPC11E68JBD48, LPC11E67JBD100, LPC11E67JBD64, LPC11E66JBD48. • • • • Section 14.6 “Connecting power, clocks, and debug functions” added. Section 14.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 22. Contents 1 2 3 4 4.1 5 5.1 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.8.1 8.8.2 8.9 8.9.1 8.9.2 8.10 8.10.1 8.11 8.11.1 8.12 8.12.1 8.13 8.13.1 8.14 8.14.1 8.15 8.15.1 8.16 8.16.1 8.17 8.17.1 8.18 8.18.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . .
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LPC11E6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.7 12.8 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 USART interface. . . . . . . . . . . . . . . . . . . . . . . SCTimer/PWM output timing . . . . . . . . . . . . . Characteristics of analog peripherals . . . . . . Application information. . . . . . . . . . . . . . . . . . ADC usage notes . . . . . . . . . . . . . . . . . . . . . . Typical wake-up times . . . . . . . . . . . . . . . . . .