Datasheet

LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 58 of 71
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
11.7.3 I/O Handler I
2
C
The I/O Handler I
2
C library allows to have an additional I
2
C-bus master. I
2
C read, I
2
C write
and combined I
2
C read/write are supported. Data is automatically read from and written to
user-defined buffers.
The I/O Handler I
2
C library combined with the on-chip I
2
C module allows to have two
distinct I
2
C buses, allowing to separate low-speed from high-speed devices or bridging
two I
2
C buses.
11.7.4 I/O Handler DMA
The I/O Handler DMA library offers DMA-like functionality. Four types of transfer are
supported: memory to memory, memory to peripheral, peripheral to memory and
peripheral to peripheral. Supported peripherals are USART, SSP0/1, ADC and GPIO.
DMA transfers can be triggered by the source/target peripheral, software, counter/timer
module CT16B1, or I/O Handler pin PIO1_6/IOH_16.