Datasheet

LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 49 of 71
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
IH
(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4] C
b
= total capacitance of one bus line in pF.
[5] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
f
.
[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[8] The maximum t
HD;DAT
could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t
VD;DAT
or
t
VD;ACK
by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system but the requirement t
SU;DAT
= 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
r(max)
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the
Standard-mode I
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Fig 23. I
2
C-bus pins clock timing
002aaf425
t
f
70 %
30 %
SDA
t
f
70 %
30 %
S
70 %
30 %
70 %
30 %
t
HD;DAT
SCL
1 / f
SCL
70 %
30 %
70 %
30 %
t
VD;DAT
t
HIGH
t
LOW
t
SU;DAT