Datasheet

LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 30 of 71
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC11Exx user manual.
7.17.6.4 APB interface
The APB peripherals are located on one APB bus.
7.17.6.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.17.6.6 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.