Datasheet

Product data sheet Rev. 2.3 — 11 September 2014 27 of 71

NXP Semiconductors

LPC11E3x

32-bit ARM Cortex-M0 microcontroller

7.17.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and

temperature is 40 % (see also Table 13

7.17.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the

CCO within its frequency range while the PLL is providing the desired output frequency.

The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The

PLL output frequency must be lower than 100 MHz. Since the minimum output divider

value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off

and bypassed following a chip reset. Software can enable the PLL later. The program

must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL

as a clock source. The PLL settling time is 100 s.

7.17.3 Clock output

The LPC11E3x feature a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.

7.17.4 Wake-up process

The LPC11E3x begin operation by using the 12 MHz IRC oscillator as the clock source at

power-up and when awakened from Deep power-down mode. This mechanism allows

chip operation to resume quickly. If the application uses the main oscillator or the PLL,

software must enable these components and wait for them to stabilize. Only then can the

system use the PLL and main oscillator as a clock source.

7.17.5 Power control

The LPC11E3x support various power control features. There are four special modes of

processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode. The CPU clock rate can also be controlled as needed by

changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider

value. This power control mechanism allows a trade-off of power versus processing speed

based on application requirements. In addition, a register is provided for shutting down the

clocks to individual on-chip peripherals. This register allows fine-tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides even

better power control.

7.17.5.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

LPC11E3x for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.