Manualshelf

Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 54
21222324252627282930
LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 22 of 71
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
7.8.1 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
• Any pin or pins in each port can trigger a port interrupt.
7.9 I/O Handler (LPC11E37HFBD64/401 only)
The I/O Handler is a software library-supported hardware engine for emulating serial
interfaces and DMA. The I/O Handler can emulate serial interfaces such as UART, I
2
C, or
I
2
S with no or very low additional CPU load. The software libraries are available with
supporting application notes from NXP (see http://www.LPCware.com.) LPCXpresso, Keil,
and IAR IDEs are supported. I/O Handler library code must be executed from the memory
area 0x2000 0000 to 0x2000 07FF. This memory is not available for other use.
For application examples, see Section 11.7 “
I/O Handler software library applications”.
7.10 USART
The LPC11E3x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.10.1 Features
• Maximum USART data bit rate of 3.125 Mbit/s.
• 16 byte receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
• Support for synchronous mode.
• Includes smart card interface.