Datasheet

Product data sheet Rev. 2.3 — 11 September 2014 21 of 71

NXP Semiconductors

LPC11E3x

32-bit ARM Cortex-M0 microcontroller

• Four programmable interrupt priority levels, with hardware priority level masking.

• Software interrupt generation.

7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but can have several

interrupt flags. Individual interrupt flags can also represent more than one interrupt

source.

7.7 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Connect peripherals to the appropriate pins before activating the peripheral and before

enabling any related interrupt. . Activity of any enabled peripheral function that is not

mapped to a related pin is treated as undefined.

7.7.1 Features

• Programmable pull-up, pull-down, or repeater mode.

• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V

= 3.3 V) if their

pull-up resistor is enabled.

• Programmable pseudo open-drain mode.

• Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to

PIO0_16. The glitch filter is turned on by default.

• Programmable hysteresis.

• Programmable input inverter.

7.8 General-Purpose Input/Output GPIO

The GPIO registers control device pin functions that are not connected to a specific

peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple

outputs can be set or cleared in one write operation.

LPC11E3x use accelerated GPIO functions:

• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved.

• Entire port value can be written in one instruction.

Any GPIO pin providing a digital function can be programmed to generate an interrupt on

a level, a rising or falling edge, or both.

The GPIO block consists of three parts:

1. The GPIO ports.

2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.

3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO

pins.