Datasheet

LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 20 of 71
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
7.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
7.6.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11E3x, the NVIC supports 24 vectored interrupts.
Fig 6. LPC11E3x memory map
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4004 C000
0x4005 8000
0x4005 C000
0x4006 0000
0x4006 4000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WWDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
USART/SMART CARD
PMU
I
2
C-bus
20 - 21 reserved
10 - 13 reserved
reserved
reserved
25 - 31 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x1000 0000
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x5000 0000
0x5000 4000
0xFFFF FFFF
reserved
reserved
reserved
2 kB SRAM2
reserved
reserved
0x4000 0000
0x4008 0000
0x4008 4000
APB peripherals
GPIO
0x2000 4000
0x2000 4800
0x1000 2000
8 kB SRAM0
LPC11E3x
0x0001 8000
96 kB on-chip flash (LPC11E36)
0x0002 0000
128 kB on-chip flash (LPC11E37)
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors
002aah405
reserved
reserved
SSP0
SSP1
16-bit counter/timer 1
16-bit counter/timer 0
IOCON
system control
19
GPIO interrupts
22
23
GPIO GROUP0 INT
24
GPIO GROUP1 INT
flash/EEPROM controller
0xE000 0000
0xE010 0000
private peripheral bus
2 kB SRAM1/
I/O Handler code area
for LPC11E37HFBD64/401
0x2000 0800