Datasheet

LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 19 of 71
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
7.3 SRAM
The LPC11E3x contain a total of 10 kB (LPC11E37HFBD64/401) or 12 kB on-chip static
RAM memory.
On the LPC11E37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to
0x2000 07FFF is used for the I/O Handler software library. Do not use this memory
location for data or other user code.
7.4 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
• IAP support for EEPROM.
• Power profiles for configuring power consumption and PLL settings.
• 32-bit integer division routines.
7.5 Memory map
The LPC11E3x incorporates several distinct memory regions, shown in the following
figures. Figure 6
shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided
to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is
512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This addressing scheme allows simplifying the address
decoding for each peripheral.