Datasheet

LPC11E3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.3 — 11 September 2014 18 of 71
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2] 5 V tolerant pad. RESET
functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 29
for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 28
).
[4] I
2
C-bus pins compliant with the I
2
C-bus specification for I
2
C standard mode, I
2
C Fast-mode, and I
2
C Fast-mode Plus.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 28
);
includes high-current output driver.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 28
); includes digital
input glitch filter.
[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). Leave XTALOUT floating.
7. Functional description
7.1 On-chip flash programming memory
The LPC11E3x contain up to 128 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages can be erased using the IAP erase page command.
7.2 EEPROM
The LPC11E3x contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM
data memory. The EEPROM can be programmed using In-Application Programming (IAP)
via the on-chip boot loader software.
XTALIN 4 4 6 8
[7]
- - Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed
1.8 V.
XTALOUT 5 5 7 9
[7]
- - Output from the oscillator amplifier.
V
DD
6; 29 6;
29
8;
44
10;
33;
48;
58
- - Supply voltage to the internal regulator, the
external rail, and the ADC. Also used as the ADC
reference voltage.
V
SS
33;
13;
14
33 5;
41
7;
54
- - Ground.
Table 3. Pin description
Symbol
Pin HVQFN33 (5x5) Pin HVQFN33 (7x7) Pin LQFP48 Pin LQFP64
Reset
state
[1]
Type Description