Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 54

1. General description

The LPC11E3x are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit

microcontroller applications, offering performance, low power, simple instruction set and

memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11E3x operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11E3x includes up to 128 kB of flash memory, up to

12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I

C-bus interface,

one RS-485/EIA-485 USART with support for synchronous mode and smart card

interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up

to 54 general purpose I/O pins.

The I/O Handler is a software library-supported hardware engine that can be used to add

performance, connectivity and flexibility to system designs. It is available on the

LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,

C, and I

S with no or very low additional CPU load and can off-load the CPU by

performing processing-intensive functions like DMA transfers in hardware. Software

libraries for multiple I/O Handler applications are available on http://www.LPCware.com.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Non Maskable Interrupt (NMI) input selectable from several input sources.

 System tick timer.

 Memory:

 Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase

(256 byte) access.

 4 kB on-chip EEPROM data memory; byte erasable and byte programmable;

on-chip API support.

 12 kB SRAM data memory.

 16 kB boot ROM.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 ROM-based 32-bit integer division routines.

LPC11E3x

32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up

to 12 kB SRAM and 4 kB EEPROM; USART

Rev. 2.3 — 11 September 2014 Product data sheet

Summary of content (71 pages)

PAGE 1
LPC11E3x 32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up to 12 kB SRAM and 4 kB EEPROM; USART Rev. 2.3 — 11 September 2014 Product data sheet 1. General description The LPC11E3x are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11E3x operate at CPU frequencies of up to 50 MHz.
PAGE 2
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller  Debug options:  Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan Description Language).  Serial Wire Debug.  Digital peripherals:  Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.  Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
PAGE 3
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller      Power-On Reset (POR).  Brownout detect with four separate thresholds for interrupt and forced reset. Unique device serial number for identification. Single 3.3 V power supply (1.8 V to 3.6 V). Temperature range 40 C to +85 C. Available as LQFP64, LQFP48, and HVQFN33 packages. 3. Applications  Consumer peripherals  Medical  Handheld scanners  Industrial control 4. Ordering information Table 1.
PAGE 4
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 4.1 Ordering options Table 2.
PAGE 5
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5.
PAGE 6
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information PIO0_19/TXD/CT32B0_MAT1 PIO0_18/RXD/CT32B0_MAT0 PIO0_17/RTS/CT32B0_CAP0/SCLK VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 31 30 29 28 27 26 25 terminal 1 index area 32 6.
PAGE 7
LPC11E3x NXP Semiconductors VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 27 26 25 PIO0_17/RTS/CT32B0_CAP0/SCLK 28 PIO0_18/RXD/CT32B0_MAT0 30 29 PIO0_19/TXD/CT32B0_MAT1 31 terminal 1 index area 32 32-bit ARM Cortex-M0 microcontroller PIO1_19/DTR/SSEL1 1 24 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE 3 22 TMS/PIO0_12/AD1/CT32B1_CAP0 XTALIN 4 21 TD
PAGE 8
LPC11E3x NXP Semiconductors 25 PIO1_31 26 PIO1_21/DCD/MISO1 27 PIO0_8/MISO0/CT16B0_MAT0 28 PIO0_9/MOSI0/CT16B0_MAT1 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 30 PIO0_22/AD6/CT16B1_MAT1/MISO1 31 PIO1_29/SCK0/CT32B0_CAP1 32 TDI/PIO0_11/AD0/CT32B0_MAT3 33 TMS/PIO0_12/AD1/CT32B1_CAP0 PIO1_14/DSR/CT16B0_MAT1/RXD 37 24 PIO1_28/CT32B0_CAP0/SCLK PIO1_22/RI/MOSI1 38 23 PIO0_7/CTS SWDIO/PIO0_15/AD4/CT32B1_MAT2 39 22 PIO0_6/SCK0 PIO0_16/AD5/CT32B1_MAT3/WAKEUP 40 21 PIO1_24/CT32B0_MAT0 VSS 41 20 n.c.
PAGE 9
LPC11E3x NXP Semiconductors 33 VDD 34 PIO1_2 35 PIO1_21 36 PIO0_8 37 PIO0_9 38 SWCLK/PIO0_10 39 PIO1_8 40 PIO0_22 41 PIO1_29 42 TDI/PIO0_11 43 PIO1_11 44 TMS/PIO0_12 45 TDO/PIO0_13 46 TRST/PIO0_14 47 PIO1_13 48 VDD 32-bit ARM Cortex-M0 microcontroller PIO1_14 49 32 PIO1_5 PIO1_3 50 31 PIO1_28 PIO1_22 51 30 PIO0_7 SWDIO/PIO0_15 52 29 PIO0_6 PIO0_16 53 28 PIO1_18 VSS 54 27 PIO1_24 PIO1_9 55 26 n.c.
PAGE 10
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and PIO0_5.
PAGE 11
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_5/SDA/IOH_3 PIO0_6/R/ SCK0/IOH_4 PIO0_7/CTS/IOH_5 PIO0_8/MISO0/ CT16B0_MAT0/R/IOH_6 PIO0_9/MOSI0/ CT16B0_MAT1/R/IOH_7 LPC11E3X Product data sheet Pin LQFP64 PIO0_4/SCL/IOH_2 Pin LQFP48 Symbol Pin HVQFN33 (7x7) Pin description Pin HVQFN33 (5x5) Table 3.
PAGE 12
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller TDI/PIO0_11/AD0/ CT32B0_MAT3 TMS/PIO0_12/AD1/ CT32B1_CAP0 TDO/PIO0_13/AD2/ CT32B1_MAT0 TRST/PIO0_14/AD3/ CT32B1_MAT1 SWDIO/PIO0_15/AD4/ CT32B1_MAT2 LPC11E3X Product data sheet Pin LQFP64 SWCLK/PIO0_10/SCK0/ CT16B0_MAT2 Pin LQFP48 Symbol Pin HVQFN33 (7x7) Pin description Pin HVQFN33 (5x5) Table 3.
PAGE 13
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_17/RTS/ CT32B0_CAP0/SCLK PIO0_18/RXD/ CT32B0_MAT0 PIO0_19/TXD/ CT32B0_MAT1 PIO0_20/CT16B1_CAP0 PIO0_21/CT16B1_MAT0/ MOSI1 LPC11E3X Product data sheet Pin LQFP64 PIO0_16/AD5/ CT32B1_MAT3/IOH_8/ WAKEUP Pin LQFP48 Symbol Pin HVQFN33 (7x7) Pin description Pin HVQFN33 (5x5) Table 3.
PAGE 14
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_23/AD7/IOH_9 PIO1_0/CT32B1_MAT0/ IOH_10 PIO1_1/CT32B1_MAT1/ IOH_11 PIO1_2/CT32B1_MAT2/ IOH_12 PIO1_3/CT32B1_MAT3/ IOH_13 PIO1_4/CT32B1_CAP0/ IOH_14 LPC11E3X Product data sheet Pin LQFP64 PIO0_22/AD6/ CT16B1_MAT1/MISO1 Pin LQFP48 Symbol Pin HVQFN33 (7x7) Pin description Pin HVQFN33 (5x5) Table 3.
PAGE 15
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO1_6/IOH_16 PIO1_7/IOH_17 PIO1_8/IOH_18 Pin LQFP64 PIO1_5/CT32B1_CAP1/ IOH_15 Pin LQFP48 Symbol Pin HVQFN33 (7x7) Pin description Pin HVQFN33 (5x5) Table 3. - - - 32 - - - - - - - - - 64 6 39 Reset state Type Description I; PU I/O PIO1_5 — General purpose digital input/output pin. - I CT32B1_CAP1 — Capture input 1 for 32-bit timer 1. - I/O IOH_15 — I/O Handler input/output 15. (LPC11E37HFBD64/401 only.
PAGE 16
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO1_16/RI/ CT16B0_CAP0 PIO1_17/CT16B0_CAP1/ RXD PIO1_18/CT16B1_CAP1/ TXD PIO1_19/DTR/SSEL1 PIO1_20/DSR/SCK1 PIO1_21/DCD/MISO1 PIO1_22/RI/MOSI1 LPC11E3X Product data sheet Pin LQFP64 PIO1_15/DCD/ CT16B0_MAT2/SCK1 Pin LQFP48 Symbol Pin HVQFN33 (7x7) Pin description Pin HVQFN33 (5x5) Table 3.
PAGE 17
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO1_24/CT32B0_MAT0 PIO1_25/CT32B0_MAT1 PIO1_26/CT32B0_MAT2/ RXD/IOH_19 PIO1_27/CT32B0_MAT3/ TXD/IOH_20 PIO1_28/CT32B0_CAP0/ SCLK PIO1_29/SCK0/ CT32B0_CAP1 Pin LQFP64 PIO1_23/CT16B1_MAT1/ SSEL1 Pin LQFP48 Symbol Pin HVQFN33 (7x7) Pin description Pin HVQFN33 (5x5) Table 3.
PAGE 18
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. Pin description Pin LQFP64 Description Pin LQFP48 Type Pin HVQFN33 (7x7) Reset state Pin HVQFN33 (5x5) Symbol XTALIN 4 4 6 8 [7] - - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5 5 7 9 [7] - - Output from the oscillator amplifier.
PAGE 19
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.3 SRAM The LPC11E3x contain a total of 10 kB (LPC11E37HFBD64/401) or 12 kB on-chip static RAM memory. On the LPC11E37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to 0x2000 07FFF is used for the I/O Handler software library. Do not use this memory location for data or other user code. 7.
PAGE 20
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC11E3x 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved 0x5000 4000 GPIO 0x5000 0000 APB peripherals reserved 0x4008 4000 reserved APB peripherals 1 GB 25 - 31 reserved 0x4008 0000 24 GPIO GROUP1 INT 0x4000 0000 23 GPIO GROUP0 INT 22 SSP1 2 kB SRAM2 0x2000 4800 19 GPIO interrupts 0x2000 4000 18 system control 17 IOCON 16 15 SSP0 flash/EEPROM controller 14 PMU reserved 0x2000 0
PAGE 21
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 7.7 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function.
PAGE 22
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.8.1 Features • • • • GPIO pins can be configured as input or output by software. All GPIO pins default to inputs with interrupt disabled at reset. Pin registers allow pins to be sensed and set individually. Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • Any pin or pins in each port can trigger a port interrupt. 7.
PAGE 23
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.11 SSP serial I/O controller The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master.
PAGE 24
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.13 10-bit ADC The LPC11E3x contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • • • • • • • • 10-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 V to VDD. 10-bit conversion time  2.44 s (up to 400 kSamples/s). Burst conversion mode for single or multiple inputs.
PAGE 25
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.15 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.16 Windowed WatchDog Timer (WWDT) The purpose of the WWDT is to prevent an unresponsive system state. If software fails to update the watchdog within a programmable time window, the watchdog resets the microcontroller 7.16.
PAGE 26
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SYSTEM CLOCK DIVIDER CPU, system control, PMU system clock n memories, peripheral clocks SYSAHBCLKCTRLn (AHB clock enable) IRC oscillator main clock SSP0 PERIPHERAL CLOCK DIVIDER SSP0 USART PERIPHERAL CLOCK DIVIDER UART SSP1 PERIPHERAL CLOCK DIVIDER SSP1 watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL (system PLL clock select) IRC oscillator system oscillator watchdo
PAGE 27
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.17.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and temperature is 40 % (see also Table 13). 7.17.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz.
PAGE 28
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. 7.17.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped.
PAGE 29
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.17.6 System control 7.17.6.1 Reset Reset has four sources on the LPC11E3x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part.
PAGE 30
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details, see the LPC11Exx user manual. 7.17.6.4 APB interface The APB peripherals are located on one APB bus. 7.17.6.
PAGE 31
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.18 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC11E3x is in reset.
PAGE 32
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD supply voltage (core and external rail) VI input voltage Conditions 5 V tolerant digital I/O pins; VDD  1.8 V Min Max Unit [2] 0.5 +4.6 V [5][2] 0.5 +5.5 V V 0.5 +3.6 [2][4] 0.5 +5.5 [2] 0.5 4.
PAGE 33
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 5. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) IDD supply current Conditions Min Typ[1] Max Unit 1.8 3.3 3.6 V - 2 - mA - 7 - mA - 1 - mA - 300 - A - 2 - A - 220 - nA Active mode; VDD = 3.
PAGE 34
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL VOL = 0.4 V 4 - - mA LOW-level output current 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.
PAGE 35
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Ipu VI = 0 V 15 50 85 A 10 50 85 A 0 0 0 A pull-up current 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V VDD < VI < 5 V I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.
PAGE 36
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2] - - 1 LSB integral non-linearity [3] - - 1.5 LSB EO offset error [4] - - 3.5 LSB EG gain error [5] - - 0.
PAGE 37
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
PAGE 38
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics Table 7. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 1 Min Typ Max Unit assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V assertion - 1.46 - V de-assertion - 1.
PAGE 39
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag749 9 48 MHz(2) IDD (mA) 6 36 MHz(2) 24 MHz(2) 3 12 MHz(1) 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled.
PAGE 40
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag751 4 IDD (mA) 3 48 MHz(2) 36 MHz(2) 2 24 MHz(2) 12 MHz(1) 1 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode.. (1) System oscillator and system PLL disabled; IRC enabled.
PAGE 41
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag746 20 IDD (µA) VDD = 3.6 V, 3.3 V VDD = 2.0 V VDD = 1.8 V 15 10 5 0 -40 -15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register. Fig 13. Typical supply current versus temperature in Power-down mode 002aag747 0.8 IDD (µA) VDD = 3.6 V VDD = 3.3 V VDD = 2.0 V VDD = 1.8 V 0.6 0.4 0.2 0 -40 -15 10 35 60 85 temperature (°C) Fig 14.
PAGE 42
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC11E3X Product data sheet Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.
PAGE 43
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.4 Electrical pin characteristics 002aae990 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 15. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aaf019 60 T = 85 °C 25 °C −40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 16.
PAGE 44
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae991 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 18.
PAGE 45
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 19. Typical pull-up current Ipu versus input voltage VI 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 20.
PAGE 46
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Nendu endurance tret retention time ter erase time tprog programming time Conditions Min [1] Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
PAGE 47
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 10.3 Internal oscillators Table 12. Dynamic characteristics: IRC Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.
PAGE 48
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 13. Dynamic characteristics: Watchdog oscillator Symbol Parameter Conditions fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register Min Typ[1] Max Unit [2][3] - 9.4 - kHz [2][3] - 2300 - kHz [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
PAGE 49
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [2] Parameters are valid over operating temperature range unless otherwise specified. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns.
PAGE 50
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.6 SSP interface Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit - - ns - - SPI master (in SPI mode) Tcy(clk) full-duplex mode [1] 50 when only transmitting [1] 40 in SPI mode [2] 15 2.0 V  VDD < 2.4 V [2] 20 1.8 V  VDD < 2.
PAGE 51
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI DATA VALID th(Q) DATA VALID tDH tDS MISO DATA VALID CPHA = 1 CPHA = 0 DATA VALID 002aae829 Fig 24. SSP master timing in SPI mode LPC11E3X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.3 — 11 September 2014 © NXP Semiconductors N.V. 2014.
PAGE 52
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 25. SSP slave timing in SPI mode LPC11E3X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.3 — 11 September 2014 © NXP Semiconductors N.V. 2014.
PAGE 53
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg).
PAGE 54
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1xxx L XTALIN XTALOUT CL = CP XTAL RS CX2 CX1 002aaf424 Fig 27. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 17.
PAGE 55
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Connect the external components to the ground plain. • To keep parasitics and the noise coupled in via the PCB as small as possible, keep loops as small as possible. • Choose smaller values of Cx1 and Cx2 if parasitics of the PCB layout increase. 11.3 Standard I/O pad configuration Figure 28 shows the possible pin modes for standard I/O pins with analog input function: • • • • • Digital output driver.
PAGE 56
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.4 Reset pad configuration VDD VDD VDD Rpu ESD 20 ns RC GLITCH FILTER reset PIN ESD VSS 002aaf274 Fig 29. Reset pad configuration 11.5 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure 30. ADC Block Source ADC COMPARATOR Rmux Rsw <2 kΩ <1.3 kΩ Cia Rs Rin Cio VEXT VSS 002aah615 Fig 30.
PAGE 57
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Under nominal operating condition VDD = 3.3 V and with the maximum sampling frequency fs = 400 kHz, the parameters assume the following values: Cia = 1 pF (max) Rmux = 2 kΩ (max) Rsw = 1.3 kΩ (max) Cio = 7.1 pF (max) The effective input impedance with these parameters is Rin = 308 kΩ. 11.
PAGE 58
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.7.3 I/O Handler I2C The I/O Handler I2C library allows to have an additional I2C-bus master. I2C read, I2C write and combined I2C read/write are supported. Data is automatically read from and written to user-defined buffers. The I/O Handler I2C library combined with the on-chip I2C module allows to have two distinct I2C buses, allowing to separate low-speed from high-speed devices or bridging two I2C buses. 11.7.
PAGE 59
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A B D terminal 1 index area E A A1 c detail X e1 e 9 16 C C A B C v w b y y1 C L 8 17 e e2 Eh 33 1 terminal 1 index area 24 32 X 25 Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23 c D(1) Dh E(1) 0.2 7.1 7.0 6.9 4.
PAGE 60
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B A terminal 1 index area A A1 E c detail X C e1 e 9 y1 C C A B C v w 1/2 e b y 16 L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 Dimensions (mm are the original dimensions) Unit(1) mm A(1) A1 b max 0.05 0.30 nom 0.85 min 0.00 0.18 c D(1) Dh E(1) Eh 5.1 3.75 5.1 3.75 0.2 4.
PAGE 61
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.
PAGE 62
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.
PAGE 63
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Soldering Footprint information for reflow soldering of HVQFN33 package Hx Gx see detail X P nSPx By Hy Gy SLy Ay nSPy C D SLx Bx Ax 0.60 solder land 0.30 solder paste detail X occupied area Dimensions in mm P Ax Ay Bx By C D Gx Gy Hx Hy SLx SLy nSPx nSPy 0.5 5.95 5.95 4.25 4.25 0.85 0.27 5.25 5.25 6.2 6.2 3.75 3.75 3 3 Issue date 11-11-15 11-11-20 002aag766 Fig 35.
PAGE 64
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of HVQFN33 package OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) W = 0.30 CU SPD = 1.00 SP LaE = 7.95 CU PIE = 7.25 PA+OA LbE = 5.80 CU evia = 4.25 evia = 1.05 0.45 DM SPE = 1.00 SP GapE = 0.70 SP 4.55 SR SEhtot = 2.70 SP EHS = 4.85 CU OwEtot = 5.10 OA OIE = 8.20 OA e = 0.65 0.45 DM GapD = 0.70 SP evia = 2.40 B-side SDhtot = 2.70 SP 4.
PAGE 65
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 37.
PAGE 66
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 38.
PAGE 67
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Revision history Table 19. Revision history Document ID Release date Data sheet status LPC11E3X v.2.3 20140911 Product data sheet Modifications: Added part LPC11E35FHI33/501. Supersedes LPC11E3X v.2.2 LPC11E3X v.2.2 20140114 Modifications: ISP mode removed from pin PIO0_3 in Table 3. LPC11E3X v.2.
PAGE 68
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 69
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 70
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 17. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . .
PAGE 71
LPC11E3x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15 15.1 15.2 15.3 15.4 16 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . .