Datasheet

Product data sheet Rev. 1.1 — 24 September 2013 25 of 62

NXP Semiconductors

LPC11E1x

32-bit ARM Cortex-M0 microcontroller

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details, see the LPC11Exx user manual.

7.16.6.4 APB interface

The APB peripherals are located on one APB bus.

7.16.6.5 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the ROM.

7.16.6.6 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.

7.17 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is

configured to support up to four breakpoints and two watch points.

The RESET

pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET

= HIGH). The ARM SWD debug port is disabled while the

LPC11E1x is in reset.

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET

pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET

pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST

pin to enable the

SWD debug mode, and release the RESET

pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.