Datasheet

Product data sheet Rev. 1.1 — 24 September 2013 17 of 62

NXP Semiconductors

LPC11E1x

32-bit ARM Cortex-M0 microcontroller

7.8.1 Features

• GPIO pins can be configured as input or output by software.

• All GPIO pins default to inputs with interrupt disabled at reset.

• Pin registers allow pins to be sensed and set individually.

• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or

level-sensitive GPIO interrupt request.

• Any pin or pins in each port can trigger a port interrupt.

7.9 USART

The LPC11E1x contain one USART.

The USART includes full modem control, support for synchronous mode, and a smart

card interface. The RS-485/9-bit mode allows both software address detection and

automatic address detection using 9-bit mode.

The USART uses a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.9.1 Features

• Maximum USART data bit rate of 3.125 Mbit/s.

• 16 byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

• Support for synchronous mode.

• Includes smart card interface.

7.10 SSP serial I/O controller

The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with

multiple masters and slaves on the bus. Only a single master and a single slave can

communicate on the bus during a given data transfer. The SSP supports full duplex

transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and

from the slave to the master. In practice, often only one of these data flows carries

meaningful data.

7.10.1 Features

• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses