Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 54

1. General description

The LPC11E1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11E1x operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11E1x includes up to 32 kB of flash memory, up to

10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I

C-bus interface,

one RS-485/EIA-485 USART with support for synchronous mode and smart card

interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC, and up

to 54 general-purpose I/O pins.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-Maskable Interrupt (NMI) input selectable from several input sources.

 System tick timer.

 Memory:

 Up to 32 kB on-chip flash program memory.

 Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.

 Up to 10 kB SRAM data memory.

 16 kB boot ROM including 32-bit integer divide routines and power profiles.

 In-System Programming (ISP) and In-Application Programming (IAP) for flash and

EEPROM via on-chip bootloader software.

 Debug options:

 Standard JTAG test interface for BSDL.

 Serial Wire Debug.

LPC11E1x

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up

to 10 kB SRAM and 4 kB EEPROM; USART

Rev. 1.1 — 24 September 2013 Product data sheet

Summary of content (62 pages)

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LPC11E1x 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USART Rev. 1.1 — 24 September 2013 Product data sheet 1. General description The LPC11E1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11E1x operate at CPU frequencies of up to 50 MHz.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller  Digital peripherals:  Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.  Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.  Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  High-current source output driver (20 mA) on one pin.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller     Unique device serial number for identification. Single 3.3 V power supply (1.8 V to 3.6 V). Temperature range 40 C to +85 C. Available as LQFP64, LQFP48, and HVQFN33 package. 3. Applications  Consumer peripherals  Medical  Handheld scanners  Industrial control 4. Ordering information Table 1.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information PIO0_19/TXD/CT32B0_MAT1 PIO0_18/RXD/CT32B0_MAT0 PIO0_17/RTS/CT32B0_CAP0/SCLK VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 31 30 29 28 27 26 25 terminal 1 index area 32 6.
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LPC11E1x NXP Semiconductors 37 PIO1_14/DSR/CT16B0_MAT1/RXD 38 PIO1_22/RI/MOSI1 39 SWDIO/PIO0_15/AD4/CT32B1_MAT2 40 PIO0_16/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO0_23/AD7 43 PIO1_15/DCD/CT16B0_MAT2/SCK1 44 VDD 45 PIO0_17/RTS/CT32B0_CAP0/SCLK 46 PIO0_18/RXD/CT32B0_MAT0 PIO1_25/CT32B0_MAT1 1 36 PIO1_13/DTR/CT16B0_MAT0/TXD PIO1_19/DTR/SSEL1 2 35 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 TMS/PIO0_12/AD1/CT32B1_CAP0 VSS 5 XTAL
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LPC11E1x NXP Semiconductors 49 PIO1_14 50 PIO1_3 51 PIO1_22 52 SWDIO/PIO0_15 53 PIO0_16 54 VSS 55 PIO1_9 56 PIO0_23 58 VDD 57 PIO1_15 59 PIO1_12 60 PIO0_17 61 PIO0_18 62 PIO0_19 63 PIO1_16 64 PIO1_6 32-bit ARM Cortex-M0 microcontroller PIO1_0 1 48 VDD PIO1_25 2 47 PIO1_13 PIO1_19 3 46 TRST/PIO0_14 RESET/PIO0_0 4 45 TDO/PIO0_13 PIO0_1 5 44 TMS/PIO0_12 PIO1_7 6 43 PIO1_11 VSS 7 42 TDI/PIO0_11 XTALIN 8 XTALOUT 9 41 PIO1_29 LPC11E14FBD64/401 40 PIO0_22 VDD 10 39 PI
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and PIO0_5.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_8/MISO0/ CT16B0_MAT0 PIO0_9/MOSI0/ CT16B0_MAT1 SWCLK/PIO0_10/SCK0/ CT16B0_MAT2 TDI/PIO0_11/AD0/ CT32B0_MAT3 TMS/PIO0_12/AD1/ CT32B1_CAP0 TDO/PIO0_13/AD2/ CT32B1_MAT0 TRST/PIO0_14/AD3/ CT32B1_MAT1 SWDIO/PIO0_15/AD4/ CT32B1_MAT2 PIO0_16/AD5/ CT32B1_MAT3/WAKEUP LPC11E1X Product data sheet LQFP64 Symbol LQFP48 Pin description HVQFN33 Table 3.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_17/RTS/ CT32B0_CAP0/SCLK LQFP64 Symbol LQFP48 Pin description HVQFN33 Table 3.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. Pin description Description LQFP64 Type LQFP48 Reset state HVQFN33 Symbol PIO1_9 - - 55 [3] I; PU I/O PIO1_9 — General purpose digital input/output pin. PIO1_10 - - 12 [3] I; PU I/O PIO1_10 — General purpose digital input/output pin. 43 [3] I; PU I/O PIO1_11 — General purpose digital input/output pin. 59 [3] I; PU I/O PIO1_12 — General purpose digital input/output pin.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO1_23/CT16B1_MAT1/ SSEL1 LQFP64 Symbol LQFP48 Pin description HVQFN33 Table 3. 13 18 24 Reset state [3] PIO1_24/CT32B0_MAT0 14 21 27 PIO1_25/CT32B0_MAT1 - 1 2 [3] 14 [3] - PIO1_27/CT32B0_MAT3/ TXD - PIO1_28/CT32B0_CAP0/ SCLK - PIO1_29/SCK0/ CT32B0_CAP1 - 11 12 24 31 15 31 41 PIO1_31 - 25 - n.c. - 19 25 n.c. - 20 26 Description I; PU I/O PIO1_23 — General purpose digital input/output pin.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 27); includes digital input glitch filter.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 On-chip flash programming memory The LPC11E1x contain 24 kB or 32 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. 7.2 EEPROM The LPC11E1x contain 500 Byte, 1 kB, 2 kB, or 4 kB of on-chip byte-erasable and byte-programmable EEPROM data memory.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC11E1x 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved APB peripherals 0x5000 4000 GPIO 25 - 31 reserved 0x5000 0000 reserved 24 GPIO GROUP1 INT 23 GPIO GROUP0 INT 22 SSP1 0x4008 0000 APB peripherals 1 GB 20 - 21 reserved 0x4000 0000 reserved 0x2000 0800 2 kB SRAM (LPC11E14/401) 0.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 7.7 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.8.1 Features • • • • GPIO pins can be configured as input or output by software. All GPIO pins default to inputs with interrupt disabled at reset. Pin registers allow pins to be sensed and set individually. Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • Any pin or pins in each port can trigger a port interrupt. 7.9 USART The LPC11E1x contain one USART.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame 7.11 I2C-bus serial I/O controller The LPC11E1x contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. 7.13 General purpose external event counter/timers The LPC11E1x include two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Optional warning interrupt can be generated at a programmable time before watchdog time-out. • Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is required to disable the WWDT. • • • • Incorrect feed sequence causes reset or interrupt, if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SYSTEM CLOCK DIVIDER CPU, system control, PMU system clock n memories, peripheral clocks SYSAHBCLKCTRLn (AHB clock enable) IRC oscillator main clock SSP0 PERIPHERAL CLOCK DIVIDER SSP0 USART PERIPHERAL CLOCK DIVIDER UART SSP1 PERIPHERAL CLOCK DIVIDER SSP1 watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator IRC oscillator system oscillator watchdog oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL (system PLL c
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.16.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.16.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.16.6 System control 7.16.6.1 Reset Reset has four sources on the LPC11E1x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details, see the LPC11Exx user manual. 7.16.6.4 APB interface The APB peripherals are located on one APB bus. 7.16.6.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit [2] 0.5 +4.6 V [5][2] 0.5 +5.5 V V supply voltage (core and external rail) VDD input voltage VI 5 V tolerant digital I/O pins; VDD  1.8 V 0.5 +3.6 [2][4] 0.5 +5.5 [2] 0.5 4.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 5. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) IDD supply current Conditions Min Typ[1] Max Unit 1.8 3.3 3.6 V - 2 - mA - 7 - mA - 1 - mA - 360 - A - 2 - A - 220 - nA Active mode; VDD = 3.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL VOL = 0.4 V 4 - - mA LOW-level output current 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter I2C-bus Conditions Min Typ[1] Max Unit pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V 3.5 - - mA 3 - - 20 - - 16 - - - 2 4 A - 10 22 A LOW-level output current IOL I2C-bus VOL = 0.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2] - - 1 LSB integral non-linearity [3] - - 1.5 LSB EO offset error [4] - - 3.5 LSB EG gain error [5] - - 0.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics Table 7. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 1 Min Typ Max Unit assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V assertion - 1.46 - V de-assertion - 1.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag749 9 48 MHz(2) IDD (mA) 6 36 MHz(2) 24 MHz(2) 3 12 MHz(1) 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag751 4 IDD (mA) 3 48 MHz(2) 36 MHz(2) 2 24 MHz(2) 12 MHz(1) 1 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag746 20 IDD (µA) VDD = 3.6 V, 3.3 V VDD = 2.0 V VDD = 1.8 V 15 10 5 0 -40 -15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register. Fig 12. Typical supply current versus temperature in Power-down mode 002aag747 0.8 IDD (µA) VDD = 3.6 V VDD = 3.3 V VDD = 2.0 V VDD = 1.8 V 0.6 0.4 0.2 0 -40 -15 10 35 60 85 temperature (°C) Fig 13.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC11E1X Product data sheet Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.4 Electrical pin characteristics 002aae990 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 14. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aaf019 60 T = 85 °C 25 °C −40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 15.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae991 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 17.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 18. Typical pull-up current Ipu versus input voltage VI 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 19.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Nendu endurance tret retention time ter erase time tprog programming time Conditions Min [1] Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 10.3 Internal oscillators Table 12. Dynamic characteristics: IRC Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %. [3] See the LPC11Exx user manual. 10.4 I/O pins Table 14. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V. Symbol Parameter tr tf [1] Conditions Min Typ Max Unit rise time pin configured as output 3.0 - 5.0 ns fall time pin configured as output 2.5 - 5.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204).
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.6 SSP interface Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit - - ns - - SPI master (in SPI mode) Tcy(clk) full-duplex mode [1] 50 when only transmitting [1] 40 in SPI mode [2] 15 2.0 V  VDD < 2.4 V [2] 20 1.8 V  VDD < 2.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 23. SSP master timing in SPI mode LPC11E1X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 24 September 2013 © NXP B.V. 2013.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 th(Q) CPHA = 0 DATA VALID 002aae830 Fig 24. SSP slave timing in SPI mode LPC11E1X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 — 24 September 2013 © NXP B.V. 2013.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg).
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1xxx L XTALIN XTALOUT = CL CP XTAL RS CX2 CX1 002aaf424 Fig 26. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 17.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Connect the external components to the ground plain. • To keep parasitics and the noise coupled in via the PCB as small as possible, keep loops as small as possible. • Choose smaller values of Cx1 and Cx2 if parasitics of the PCB layout increase. 11.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.4 Reset pad configuration VDD VDD VDD Rpu ESD 20 ns RC GLITCH FILTER reset PIN ESD VSS 002aaf274 Fig 28. Reset pad configuration 11.5 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure 29. ADC Block Source ADC COMPARATOR Rmux Rsw <2 kΩ <1.3 kΩ Cia Rs Rin Cio VEXT VSS 002aah615 Fig 29.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Under nominal operating condition VDD = 3.3 V and with the maximum sampling frequency fs = 400 kHz, the parameters assume the following values: Cia = 1 pF (max) Rmux = 2 kΩ (max) Rsw = 1.3 kΩ (max) Cio = 7.1 pF (max) The effective input impedance with these parameters is Rin = 308 kΩ. 11.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A B D terminal 1 index area E A A1 c detail X e1 e 9 16 C C A B C v w b y y1 C L 8 17 e e2 Eh 33 1 terminal 1 index area 24 32 X 25 Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23 c D(1) Dh E(1) 0.2 7.1 7.0 6.9 4.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Soldering Footprint information for reflow soldering of HVQFN33 package OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) W = 0.30 CU SPD = 1.00 SP LaE = 7.95 CU PIE = 7.25 PA+OA LbE = 5.80 CU evia = 4.25 evia = 1.05 0.45 DM SPE = 1.00 SP GapE = 0.70 SP 4.55 SR SEhtot = 2.70 SP EHS = 4.85 CU OwEtot = 5.10 OA OIE = 8.20 OA e = 0.65 0.45 DM GapD = 0.70 SP evia = 2.40 B-side SDhtot = 2.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 34.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 35.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations Table 19.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11E1X v.1.1 20130924 Product data sheet - LPC11E1X v.1 Modifications: • • • • • • • Parameters ter and fclk removed in Table 10. Table 3: Added “5 V tolerant pad” to RESET/PIO0_0 table note. Table 7: Removed BOD interrupt level 0. Added Section 11.5 “ADC effective input impedance”.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC11E1x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 18. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . .