Datasheet

LPC11D14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 23 July 2012 35 of 47
NXP Semiconductors
LPC11D14
32-bit ARM Cortex-M0 microcontroller
[1] T
cy(clk)
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the
main clock frequency f
main
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] T
amb
= 40 C to +85 C.
[3] T
cy(clk)
= 12  T
cy(PCLK)
.
[4] T
amb
= 25 C; for normal voltage supply range: V
DD
= 3.3 V.
SPI slave (in SPI mode)
T
cy(PCLK)
PCLK cycle time 20 - - ns
t
DS
data set-up time in SPI mode
[3][4]
0-- ns
t
DH
data hold time in SPI mode
[3][4]
3  T
cy(PCLK)
+ 4 - - ns
t
v(Q)
data output valid time in SPI mode
[3][4]
--3  T
cy(PCLK)
+ 11 ns
t
h(Q)
data output hold time in SPI mode
[3][4]
--2  T
cy(PCLK)
+ 5 ns
Table 17. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 21. SPI master timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
T
cy(clk)
t
clk(H)
t
clk(L)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID
DATA VALID
MOSI
MISO
t
DS
t
DH
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
t
v(Q)
CPHA = 1
CPHA = 0
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