Datasheet

LPC11D14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 23 July 2012 14 of 47
NXP Semiconductors
LPC11D14
32-bit ARM Cortex-M0 microcontroller
Remark: Do not transfer data on the I
2
C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2.4 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between V
LCD
and V
SS(LCD)
. The middle resistor
can be bypassed to provide a 1/2 bias voltage level for the 1:2 multiplex configuration.
The LCD voltage can be temperature compensated externally using the supply to pin
V
LCD
.
7.2.5 Oscillator
7.2.5.1 Internal clock
The internal logic of the PCF8576D and the LCD drive signals are timed by the internal
oscillator. The internal oscillator is always enabled. The output from pin CLK can be used
as the clock signal for several PCF8576Ds in the system that are connected in cascade.
7.2.6 Timing
The PCF8576D timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF8576D in the system is
maintained by the synchronization signal at pin SYNC
. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency (f
fr
) is a fixed division of the clock frequency (f
clk
) from either the internal or an
external clock: f
fr
= f
clk
/24.
7.2.7 Display register
A display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs, and each column of the display RAM.
7.2.8 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display latch. When less than
40 segment outputs are required, the unused segment outputs should be left open-circuit.
7.2.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals
and may also be paired to increase the drive capabilities.