Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 ARM Cortex-M0 processor
- 7.2 On-chip flash program memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Nested Vectored Interrupt Controller (NVIC)
- 7.6 IOCONFIG block
- 7.7 Fast general purpose parallel I/O
- 7.8 UART
- 7.9 SPI serial I/O controller
- 7.10 I2C-bus serial I/O controller
- 7.11 C_CAN controller
- 7.12 10-bit ADC
- 7.13 General purpose external event counter/timers
- 7.14 System tick timer
- 7.15 Watchdog timer
- 7.16 Clocking and power control
- 7.17 System control
- 7.18 Emulation and debugging
- 8. Limiting values
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Application information
- 12. Package outline
- 13. Soldering
- 14. Abbreviations
- 15. Revision history
- 16. Legal information
- 17. Contact information
- 18. Contents

NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 May 2013
Document identifier: LPC11CX2_CX4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 57
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 58
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 59
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 59
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
17 Contact information. . . . . . . . . . . . . . . . . . . . . 60
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61