Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 ARM Cortex-M0 processor
- 7.2 On-chip flash program memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Nested Vectored Interrupt Controller (NVIC)
- 7.6 IOCONFIG block
- 7.7 Fast general purpose parallel I/O
- 7.8 UART
- 7.9 SPI serial I/O controller
- 7.10 I2C-bus serial I/O controller
- 7.11 C_CAN controller
- 7.12 10-bit ADC
- 7.13 General purpose external event counter/timers
- 7.14 System tick timer
- 7.15 Watchdog timer
- 7.16 Clocking and power control
- 7.17 System control
- 7.18 Emulation and debugging
- 8. Limiting values
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Application information
- 12. Package outline
- 13. Soldering
- 14. Abbreviations
- 15. Revision history
- 16. Legal information
- 17. Contact information
- 18. Contents
LPC11CX2_CX4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3.1 — 15 May 2013 53 of 62
NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
11.5 Reset pad configuration
11.6 C_CAN with external transceiver (LPC11C12/C14 only)
Fig 26. Reset pad configuration
V
SS
reset
002aaf274
V
DD
V
DD
V
DD
R
pu
ESD
ESD
20 ns RC
GLITCH FILTER
PIN
Fig 27. Connecting the C_CAN to an external transceiver (LPC11C12/C14)
S
TXD
RXD
LPC11C12/C14
PIOx_y
CAN_TXD
CAN_RXD
GND
V
CC
CANH
CANH
CANL
CANL
5 V
BAT
3 V
V
IO
002aaf911
TJF1051