Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 ARM Cortex-M0 processor
- 7.2 On-chip flash program memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Nested Vectored Interrupt Controller (NVIC)
- 7.6 IOCONFIG block
- 7.7 Fast general purpose parallel I/O
- 7.8 UART
- 7.9 SPI serial I/O controller
- 7.10 I2C-bus serial I/O controller
- 7.11 C_CAN controller
- 7.12 10-bit ADC
- 7.13 General purpose external event counter/timers
- 7.14 System tick timer
- 7.15 Watchdog timer
- 7.16 Clocking and power control
- 7.17 System control
- 7.18 Emulation and debugging
- 8. Limiting values
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Application information
- 12. Package outline
- 13. Soldering
- 14. Abbreviations
- 15. Revision history
- 16. Legal information
- 17. Contact information
- 18. Contents
LPC11CX2_CX4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3.1 — 15 May 2013 50 of 62
NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
11. Application information
11.1 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 7
:
• The ADC input trace must be short and as close as possible to the LPC11Cx2/Cx4
chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
C
i
= 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground C
g
which attenuates the input voltage by a factor C
i
/(C
i
+ C
g
). In slave
mode, a minimum of 200 mv (RMS) is needed.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 23
), with an amplitude between 200 mv (RMS) and 1000 mv (RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 24
and in
Table 19
and Table 20. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances C
X1
and C
X2
need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, C
L
and
R
S
). Capacitance C
P
in Figure 24 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters F
OSC
, C
L
, R
S
and C
P
are supplied by the crystal
manufacturer (see Table 19
).
Fig 23. Slave mode operation of the on-chip oscillator
LPC1xxx
XTALIN
C
i
100 pF
C
g
002aae788