Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 ARM Cortex-M0 processor
- 7.2 On-chip flash program memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Nested Vectored Interrupt Controller (NVIC)
- 7.6 IOCONFIG block
- 7.7 Fast general purpose parallel I/O
- 7.8 UART
- 7.9 SPI serial I/O controller
- 7.10 I2C-bus serial I/O controller
- 7.11 C_CAN controller
- 7.12 10-bit ADC
- 7.13 General purpose external event counter/timers
- 7.14 System tick timer
- 7.15 Watchdog timer
- 7.16 Clocking and power control
- 7.17 System control
- 7.18 Emulation and debugging
- 8. Limiting values
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Application information
- 12. Package outline
- 13. Soldering
- 14. Abbreviations
- 15. Revision history
- 16. Legal information
- 17. Contact information
- 18. Contents

LPC11CX2_CX4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3.1 — 15 May 2013 34 of 62
NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
9.2 C_CAN on-chip, high-speed transceiver characteristics
Table 8. Static characteristics
T
amb
= 40 C to +85 C; V
CC
= 4.5 V to 5.5 V; R
L
=60; unless otherwise specified; all voltages are defined with respect to
ground; positive currents flow into the IC. Also see Figure 28.
Symbol Parameter Conditions Min Typ Max Unit
Supply; pin VCC
V
CC
supply voltage 4.5 - 5.5 V
I
CC
supply current Silent mode 0.1 1 2.5 mA
Normal mode
recessive 2.5 5 10 mA
dominant; CAN_TXD = LOW 20 50 70 mA
V
uvd(VCC)
undervoltage detection
voltage on pin V
CC
3.5 - 4.5 V
I/O level adapter supply; pin VDD_CAN
V
DD
supply voltage on pin VDD_CAN
[1]
2.8 - 5.5 V
I
DD
supply current on pin VDD_CAN; Normal and Silent
modes
recessive; CAN_TXD = HIGH 10 80 250 A
dominant; CAN_TXD = LOW 50 350 500 A
V
uvd(VDD_CAN)
undervoltage detection
voltage on pin VDD_CAN
1.3 - 2.7 V
Mode control input; pin STB
V
IH
HIGH-level input voltage 0.7V
CC
-V
CC
+0.3 V
V
IL
LOW-level input voltage 0.3 - 0.3V
CC
V
I
IH
HIGH-level input current 1 4 10 A
I
IL
LOW-level input current Voltage on pin STB = 0 V 10+1 A
Bus lines; pins CANH and CANL
V
O(dom)
dominant output voltage CAN_TXD = LOW; t < t
to(dom)TXD
pin CANH 2.75 3.5 4.5 V
pin CANL 0.5 1.5 2.25 V
V
dom(TX)sym
transmitter dominant voltage
symmetry
V
dom(TX)sym
= V
CC
V
CANH
V
CANL
400 0 +400 mV
V
O(dif)bus
bus differential output
voltage
CAN_TXD = LOW; t < t
to(dom)TXD
1.5 - 3 V
CAN_TXD = HIGH; recessive;
no load
50 - +50 mV
V
O(rec)
recessive output voltage Normal and Silent modes;
CAN_TXD = HIGH; no load
20.5V
CC
3V
V
th(RX)dif
differential receiver
threshold voltage
Normal and Silent modes
V
cm(CAN)
[2]
= 12 V to +12 V
0.5 0.7 0.9 V
V
hys(RX)dif
differential receiver
hysteresis voltage
Normal and Silent modes
V
cm(CAN)
= 12 V to +12 V
50 120 400 mV
I
O(dom)
dominant output current CAN_TXD = LOW; t < t
to(dom)TXD
;
V
CC
=5 V
pin CANH; V
CANH
=0V 120 70 40 mA
pin CANL; V
CANL
= 5 V/40 V 40 70 120 mA