Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 ARM Cortex-M0 processor
- 7.2 On-chip flash program memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Nested Vectored Interrupt Controller (NVIC)
- 7.6 IOCONFIG block
- 7.7 Fast general purpose parallel I/O
- 7.8 UART
- 7.9 SPI serial I/O controller
- 7.10 I2C-bus serial I/O controller
- 7.11 C_CAN controller
- 7.12 10-bit ADC
- 7.13 General purpose external event counter/timers
- 7.14 System tick timer
- 7.15 Watchdog timer
- 7.16 Clocking and power control
- 7.17 System control
- 7.18 Emulation and debugging
- 8. Limiting values
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Application information
- 12. Package outline
- 13. Soldering
- 14. Abbreviations
- 15. Revision history
- 16. Legal information
- 17. Contact information
- 18. Contents
LPC11CX2_CX4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3.1 — 15 May 2013 32 of 62
NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[15] To V
SS
.
9.1 ADC characteristics
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See Figure 6.
[3] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 6
.
[4] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 6
.
[5] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 6
.
[6] The absolute error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 6
.
[7] T
amb
= 25 C; maximum sampling frequency f
s
= 400 kSamples/s and analog input capacitance C
ia
= 1 pF.
[8] Input resistance R
i
depends on the sampling frequency fs: R
i
= 1 / (f
s
C
ia
).
Table 7. ADC static characteristics
T
amb
=
40
C to +85
C unless otherwise specified; ADC frequency 4.5 MHz, V
DD
= 2.5 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
V
IA
analog input voltage 0 - V
DD
V
C
ia
analog input capacitance - - 1 pF
E
D
differential linearity error
[1][2]
-- 1LSB
E
L(adj)
integral non-linearity
[3]
-- 1.5 LSB
E
O
offset error
[4]
-- 3.5 LSB
E
G
gain error
[5]
--0.6%
E
T
absolute error
[6]
-- 4LSB
R
vsi
voltage source interface
resistance
--40k
R
i
input resistance
[7][8]
--2.5M