Datasheet

Table Of Contents
LPC11CX2_CX4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3.1 — 15 May 2013 16 of 62
NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
Controls system exceptions and peripheral interrupts.
In the LPC11Cx2/Cx4, the NVIC supports 32 vectored interrupts including 13 inputs to
the start logic from individual GPIO pins.
Fig 4. LPC11Cx2/Cx4 memory map
0x5000 0000
0x5001 0000
0x5002 0000
0x5020 0000
AHB peripherals
16 - 127 reserved
GPIO PIO1
4-7
0x5003 0000
0x5004 0000
GPIO PIO2
GPIO PIO3
8-11
12-15
GPIO PIO0
0-3
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 0000
0x4005 4000
0x4005 8000
0x4005 C000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
UART
PMU
I
2
C-bus
10 - 13 reserved
reserved
reserved
reserved
23 - 31 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x1000 2000
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x4000 0000
0x4008 0000
0x5000 0000
0x5020 0000
0xFFFF FFFF
reserved
reserved
reserved
APB peripherals
AHB peripherals
0x1000 0000
8 kB SRAM
LPC11Cx2/Cx4
0x0000 4000
16 kB on-chip flash (LPC11Cx2)
0x0000 8000
32 kB on-chip flash (LPC11Cx4)
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors
002aaf268
reserved
SPI0
16-bit counter/timer 1
16-bit counter/timer 0
IOCONFIG
system control
20
19
C_CAN
reserved
22
21
SPI1
flash controller
0xE000 0000
0xE010 0000
private peripheral bus